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|Overview | Control Unit | Microcode Header | Arithmetic Unit | Data Registers | Address Registers | Expansion Bus|
Last updated: 2012-05-07
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The Microcode Upload Header sits on top of the Control Unit and enables the download of microcode into the rams of the CPU via a serial link, in addition to the microcode eproms.
Initially it was not planned to replace the microcode without changing the eproms. But there showed to be a very simple way to load data from another source than the 3 eproms ontop of the control unit.
The code from the eproms is copied into fast rams after reset. It is possible to supply data from another source instead, if the eproms are disabled. This is very easy for the Front Panel to do, because it has full control over CPU reset and the CPU's main clock.
The idea is to put an "upload header" into the eprom sockets, which contains serial-to-parallel shift registers instead of the eproms. Now the front panel can reset the CPU, then increment the system clock slowly, and with every CPU clock cycle shift new data into the shift registers, and when the new data is present at the shift register outputs, step the main clock one step further, so that the data is loaded into the microcode rams, as if it were loaded from the eproms. When data for all 32k addresses are copied, the control unit of the CPU switches to execution mode and starts executing the microcode. Now the front panel must disable the shift register outputs and can release control over the CPU main clock and the CPU will run and execute the supplied code instead of the eproms code.
It is not neccessary to remove the eproms entirely. Instead they can be placed on the upload header in the inter-board connector sockets. Only the /OE lines from the control unit must be cut and the eproms' /OE is now controlled on the upload header instead. This way either the original eproms can be loaded or data from the serial link, which is connected to the front panel of the computer.
The microcode upload header is controlled by 4 lines:
• shift clock
• serial data
• parallel data latch strobe
• shift register output enable
The shift registers are three 74HC595 8-bit shift registers with output register and 3-state output control. The serial data output of one shift register is connected to the serial data input of the next shift register. This way 24 bit serial data are shifted through all three shift registers. Then a pulse on the parallel data latch strobe transfers the data into the output registers.
If the shift register output enable is low, then the shift register data is placed on the microcode data bus, while the eproms' output enables are forced high via the discrete inverter, so that they stay inactive.
note: It is possible to enable the shift register outputs while the CPU is running and the microcode rams put their data on the microcode data bus as well. Of course this must be avoided!
Placement of the sockets and most other parts were determined by the eprom sockets and space around them on the control unit.
The blocking capacitors on the control unit are reused for the shift register ICs and eproms on the upload header.
The control lines are not accompanied by GND or Vcc leads. 4 lines were just enough. B-)
If the control lines are not connected, the input lines are pulled high by a resistor network, so that the upload header can still remain in place.
Finally, i am afraid that the add-on height might not fit into the case. :-/
Update: it fits in! Less than a mm space left... :-)
size: 1023 × 574
|Board rear 1.4.pdf||2010-02-22 17:14||41065|
|Board top 1.4.pdf||2010-02-22 17:14||114525|
size: 1005 × 544
|Component placement 1.4.pdf||2010-02-22 17:14||6318|
|Proghead 1.4.brd||2010-02-22 17:08||45694|
|Proghead 1.4.sch||2010-02-22 15:42||33120|
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