Last updated: 2012-05-07
Questions & comments to Kio
2012-03-16: soldering the SIO board. I have used the wrong SO-8 package for the board layout and had to place the I2C EEprom very carefully on the PCB to solder it. The pins extended beyond the solder pads, but it seemed to work.
2012-03-17: Heart attack: i took a look at the SIO's data sheet and saw that pins were numbered starting at a corner. X-( .... but this was for the TQFP-44 package. Pin numbers of the PLCC package start in the middle of one side. HTF were these brain dead idiots... ? I still don't know whether this will work at all. Testing starts soon...
2012-05-07: I have tested the board and it works ok. Only the i2c eeprom refuses to respond. This needs further examinations.
The preliminary SIO board is built around a 88C192 dual UART with 16 byte internal FIFO. It is clocked with 7.372 MHz and connected to the K1 I/O bus in a plain vanilla way. The two serial ports are exposed to a 3.5mm stereo jack, a 6-pin Mini-DIN connector and a 4-pin jumper each. The 4 inputs and outputs require 5V CMOS levels and are driven by 4 OR and 4 XOR gates. If a plug is plugged in the stereo jack, the Mini-DIN socket and the pin header are disabled. The Mini-DIN sockets carry hardware flow control lines which can be programmed to be used as clock lines alternatively. The 4-pin header features an extra 'control' line output (which i happen to need for connecting the front panel to the K1-16/16 CPU).
My originally ordered board had an error with the package of the EEprom. I used a 'SO-08 SN' type in the drawing while i actually have 'SO-08 SM' types in stock. But i was able to solder the EEprom nethertheless. The error is fixed in the board version v1.1.
K1 Bus Connection
The board has a jumper array JP1,JP2 to select the board's address from 4 randomly choosen addresses in range 1 to 14. This is done by connecting the board's 'MY_DATA' line with a jumper to one of the randomly choosen data lines of the K1 bus.
The host CPU selects a board by putting a word with only one '0'-bit on the K1 data bus and strobing control line 'SELECT' low. This latches the state of 'MY_DATA' line into the select flip flop and the state remains persistent at it's '!SELECTED' output. Any subsequent communication on the K1 bus is with the selected board only.
Similarly an interrupt-enable state '!INT_EN' is written to the board by strobing control line 'WR_IRPT' low. This enables the driver IC6C (1/4 74HC125) which drives the state of the 88C192's '!INT' output to driver IC6B which emulates an open collector output which is connected to the K1 bus 'IRPT' sensor line. This works independently from the '!SELECTED' state.
The host CPU can read the interrupt state of all attached boards, whether their interrupts are enabled or not and whether they are currently selected or not, by reading a data word from the K1 bus with control signal 'RD_IRPT'. This enables driver IC6A which puts the 88C192's interrupt ouput on 'MY_DATA' line.
An I2C EEprom is connected to the I2C_DATA and I2C_CLOCK lines of the K1 bus. This is meant to provide a device driver in hardware-independent byte code. The A0 address line of the EEprom is connected to the board's '!SELECTED' state. If '!SELECTED' is true (0) then A0 of the EEprom is 0 and the EEprom reacts to commands to I2C address 0x00. Else it does not react to commands to address 0x00. The host cpu selects a board prior to I2C communication and only the selected board's EEprom reacts to I2C communication with address 0x00.
Though not strictly neccessary, this board has a 74AC245 bus driver between the 8 data lines of the UART and the K1 bus. The major reason for this is, that the 88C192 has TTL input and output levels, while the K1 bus per definition uses CMOS levels.
The driver is enabled when the board is selected by connecting '!SELECTED' to the '!OE' input. While there is no data transfer going on or while the host CPU is writing data to the UART strobing control line 'WR_DATA' low, the driver drives in direction K1 bus -> UART. The direction is only reverted when the host CPU reads data by strobing control line 'RD_DATA' low. There will be a short moment of bus collission between the 74AC245 driver and the UART when the 'RD_DATA' strobe turns off, because the 88C192 has a switch-off delay of up to 20µs while the 74AC245 is faster. But the driver will drive back for a tiny moment what it just has driven outwards until other data is put on the bus or the host CPU's pullup resistors settle the data lines to a new value, so there is actually no real collission, hopefully.
The 88C192 UART is clocked with 7.372 MHz which doubles all values documented for the 'standard' 3.6864 MHz crystal. The UART is promissed to work up to 16 MHz, i hope this includes it's own crystal oscilator as well.
The 88C192 has a very limited set of SIO clocks it can generate. First, you have to choose one of two tables, which applies to both serial connections. So this is a design decission and can't be easily changed at run time, because you never know whether the 'other' channels baud rate is in the table you select for 'this' channel. Then it's a crude mixture of baud rates, though the majority is from the 'multiple of 300' series and the 'multiple of 450' series. Next, for each channel you must choose one of 3 sub tables with at most 14 entries each. Now you can pick your sender and receiver clock from this table independently. This is a feature from the stone age of serial communication and i don't plan to support it. The available baud rates for both 'global' tables (after multiplying with 2 and after removing double entries) are:
I opted for table ACR.7=0.
Serial Port Connections
Both, channel A and B, are exposed in the same way to 3 possible connectors each:
The 3.5mm jack is the first choice. It has built-in switches which are disconnected when a plug is plugged in. If no plug is plugged in the 3.5mm jacks, then the Mini-DIN or the 4-pin header can be used.
The 3.5mm jack only carries the TxD and RxD signal.
The 4-pin header also has a 'control' line which is connected to an output port of the UART directly.
The 6-pole Mini-DIN socket also carries 2 additional hardware flow control or clock lines and the +5V supply to power an external low-power device.
All output signals are 'filtered' with an 68Ω series resistor. All input signals are protected with a 1k5Ω series resistor and pulled low with an 22kΩ resistor. Pulling low the RxD line by default may be a little problem, because this is the 'mark' position and will be interpreted as a 'break'. But this way you know whether a remote device is connected or not.
TxD and RxD are driven through 74HC32 OR gates, which convert between CMOS levels (on the serial line) and TTL levels (of the UART) and add some more driving power to the output lines.
RTS and CLK outputs are combined with and driven by 74HC86 XOR gate to the RxD control output lines. This allows this line to be used for RTS or for a clock signal, either inverted or not. It just depends on which port you actually use while you keep the other port at a fixed level.
CTS, RxCLK and TxCLK inputs are all connected to the output of one XOR gate which reads the TxD control input line. The XOR gate can be toggled by just another output pin. So this line can be used for CTS or for an external clock which may be inverted, depending on the other input to the XOR gate.
|2012-02-03 board components.png
size: 915 × 722
|2012-02-03 board rear.png
size: 915 × 723
|2012-02-03 board top.png
size: 915 × 722
size: 1702 × 828
|2012-03-16 board populated.jpg
size: 810 × 632
size: 817 × 635
|2012-03-16 finished board.jpg
size: 835 × 584
size: 853 × 476
|2012-03-18 circuit.pdf||2012-03-18 13:47||60505|
|8892,88192 [C] Dual UART with 8:16 byte fifo.pdf||2007-06-16 20:57||195161|
|SIO board rear.jpg
size: 778 × 625
|SIO board top.jpg
size: 780 × 626
|SIO component placement.pdf||2012-03-16 17:04||42491|
|SIO part list.txt||2012-03-13 16:39||521|
|SIO v1.1.brd||2012-03-18 13:44||56008|
|SIO v1.1.sch||2012-03-18 13:45||125442|
|SIO v1.2.b#1||2012-03-18 13:44||56008|
|SIO v1.2.brd||2012-05-14 20:19||56176|
|SIO v1.2.s#1||2012-03-18 13:45||125442|
|SIO v1.2.sch||2012-05-14 20:19||125706|
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