I.2.1 The GAL16V8 and GAL20V8
There are several types of GAL16V8 and GAL20V8 GALs, the standard-, A- and
B-type GAL16V8, GAL20V8. The A- and B-type GALs needs less power and are
faster. But since there is no greate difference between them I will only
talk about the standard GALs GAL16V8 and GAL20V8. When there are any
differences between A-, B- and standard-GALs I will mention this extra.
At first the pin designations:
GAL16V8
---- ----
Input or Clock 1| |20 +5V
Input 2| |19 Configurable Output Cell
Input 3| |18 Configurable Output Cell
Input 4| |17 Configurable Output Cell
Input 5| |16 Configurable Output Cell
Input 6| |15 Configurable Output Cell
Input 7| |14 Configurable Output Cell
Input 8| |13 Configurable Output Cell
Input 9| |12 Configurable Output Cell
GND 10| |11 Input or /OE
---------
GAL20V8
---- ----
Input or Clock 1| |24 +5V
Input 2| |23 Input
Input 3| |22 Configurable Output Cell
Input 4| |21 Configurable Output Cell
Input 5| |20 Configurable Output Cell
Input 6| |19 Configurable Output Cell
Input 7| |18 Configurable Output Cell
Input 8| |17 Configurable Output Cell
Input 9| |16 Configurable Output Cell
Input 10| |15 Configurable Output Cell
Input 11| |14 Input
GND 12| |13 Input or /OE
---------
From the pin designations you can see that the only difference between the
GAL16V8 and GAL20V8 is the number of inputs. The choice of GAL then, is
dependant solely on the number of required inputs.
The essential part of every GAL is a logic-matrix. The input pins of the
GAL are connected both inverted and uninverted to the columns of this matrix.
If the GAL hasn't been programmed the rows and columns are connected to
each other. Every connection between a row and a column represents an
AND gate. If the GAL is programmed the particular connections are erased
so that the wanted logic is programmed. A row is called a product term,
because every column (input) that is still connected to a row represents
an AND gate.
Eight of these rows (product terms) of a GAL16V8 or GAL20V8 are connected
with the so called OLMC (Output Logic Macro Cell). In this OLMC the
product terms are ORed together. The OLMC is a "configurable output cell".
What is a "Configurable Output Cell"?
A GAL16V8 or GAL20V8 contains eight of these configurable output cells. These
output cells may be configured as input, combinational output, tristate output,
or register output.
Combinational Output: This output can be HIGH or LOW.
Tristate Output: This output can take one of three states:
HIGH, LOW, and HIGH IMPEDANCE
This is used if you want to tie two outputs together,
but only one may be active.
Register Output: With this output the result of an equation is not
directly coupled to the output, but connected via
a D-FlipFlop. Only on receipt of a clock pulse, is
the signal passed to the output. When /OE is HIGH,
then the output goes HIGH-IMPEDANCE.
Besides the matrix, a GAL16V8, GAL20V8 contains extra bits:
( (n) means that these bits are available for each output).
XOR (n) : The result of the digital connection can be negated with this bit.
XOR (n) = 0 : Output is active LOW
XOR (n) = 1 : Output is active HIGH
SYN, AC0, AC1(n):
These bits determine in which mode the GAL works. Mode means, which type
of outputs are used (register, tristate,...). There are three main
operating modes in which the GAL works:
Mode 1: SYN = 1, AC0 = 0
AC1(n) = 1 : OLMC as input
AC1(n) = 0 : OLMC as combinational output
Mode 2: SYN = 1, AC0 = 1
AC1(n) = 1 : tristate output
Mode 3: SYN = 0, AC0 = 1
AC1(n) = 1 : OLMC as tristate output
AC1(n) = 0 : OLMC as register output
PT0...63: (PT = product term)
These bits indicate whether the rows (product terms) 0...63 in the
GAL's matrix are valid or not.
PTx = 1: AND-junction in the row x is valid.
PTx = 0: AND-junction in the row x is not used (have no effect) on
the output.
(x = between 0 and 63; there are 64 rows in the matrix,
so that each row can be individually activated or deactivated)
All these bits (82 bits) are tied together via the so called Architecture-
Control-Word (ACW). The ACW is described in chapter III.
Signature:
Here are eight bytes for your own use. Normally a short comment or
a version number of the GAL is placed here.
Security fuse: (Security-Bit)
By setting this bit the GAL can be protected from unauthorized copying.
The reading of the logic matrix is no longer possible. Since the rest of
the bits can still be read this protection is not very effective.
Bulk Erase:
By programming this row the whole GAL is erased. Now it is possible to
program the GAL again. A GAL can be reprogrammed about 100 times.
The Operation Modes of a GAL16V8 and GAL20V8
As already explained the SYN, AC0 and AC1(n) bits determine the mode
of the GAL. The pin designations of the GAL are determined by this mode.
GAL16V8:
Mode 1 | Mode 2 | Mode 3 Mode 1 | Mode 2 | Mode 3
--------------------------- --------------------------
| | --- --- | |
In | In | Clock 1| |20 +5V | +5V | +5V
In | In | In 2| |19 In/C | T* | In/T/R
In | In | In 3| |18 In/C | In/T | In/T/R
In | In | In 4| |17 In/C | In/T | In/T/R
In | In | In 5| |16 C | I/T | In/T/R
In | In | In 6| |15 C | In/T | In/T/R
In | In | In 7| |14 In/C | In/T | In/T/R
In | In | In 8| |13 In/C | In/T | In/T/R
In | In | In 9| |12 In/C | T* | In/T/R
GND | GND | GND 10| |11 In | In | /OE
-------
GAL20V8:
Mode 1 | Mode 2 | Mode 3 Mode 1 | Mode 2 | Mode 3
--------------------------- --------------------------
| | --- --- | |
In | In | Clock 1| |24 +5V | +5V | +5V
In | In | In 2| |23 In | In | In
In | In | In 3| |22 In/C | T* | In/T/R
In | In | In 4| |21 In/C | In/T | In/T/R
In | In | In 5| |20 In/C | In/T | In/T/R
In | In | In 6| |19 C | In/T | In/T/R
In | In | In 7| |18 C | In/T | In/T/R
In | In | In 8| |17 In/C | In/T | In/T/R
In | In | In 9| |16 In/C | In/T | In/T/R
In | In | In 10| |15 In/C | T* | In/T/R
In | In | In 11| |14 In | In | In
GND | GND | GND 12| |13 In | In | /OE
-------
Abbreviations:
In : input
C : combinational output without feedback
T : tristate-output
T* : tristate-output without freedback to the matrix, which means
that this output cannot be configured as input
R : register-output
Clock : pulse for D-FlipFlops; only affects those pins which are
configured as register-output
/OE : output enable (low active): activate the register-outputs
(see I.2)
From the pin designations you can see that pins 15 and 16 of the GAL16V8
and pins 18 and 19 of GAL20V8 cannot be programmed as inputs when the GAL is
in mode 1. The same hold true for pins 12 and 19 and 15 and 22 for mode 2.
In mode 1, pins 1 and 11 (GAL16V8) and pins 1 and 13 (GAL20V8) are reserved
for Clock and /OE. These pins therefore cannot be used as inputs.
As I told, eight of the rows (product terms) of a GAL16V8 or GAL20V8 are
connected via an OR gate to the OLMC. This means that you can use eight
product terms to define your output. But when using a tristate output, one
row of these eight rows is needed for the tristate control. So you use
only seven product terms for tristate output definitions.
Here some sentences to the mode, which should make it easier to you to
understand what mode is used:
If you need at least one register output in your GAL, then mode 3 is used.
When you need at least one tristate output and no register output, then the
GAL will be in mode 2. When you need neither a tristate nor a register
output, mode 1 is used.