Note: these are the logical equations to describe the connections of the different chips on the board
written down when i analyzed the circuit in 2015.
They are not the source for the GAL which can be found in "gal.asm".

	Kio !


IC7A = FF_HIDE		-> MF3 visible/invisible
IC3A = FF_NMI 		-> NMI pending
IC9B = FF_ALLRAM 	-> MMU special mode: normal/all_ram
IC3B = FF_PAGE 		-> MF3 memory paged in/out


PAL.WPORTxFFD pin17 = !( !IORQ + !WR + %---1.----.11111101 )
PAL.WPORT     pin18 = !( !IORQ + !WR + %-011.1111 )
PAL.RPORT     pin19 = !( !IORQ + !RD + %-011.1111 + (A7 | !FF_HIDE) )
PAL.CONMEM    pin12 = !( !MREQ + !RD + !M1 + %0000.0000.01100110 + FF_NMI + !FF_ALLRAM )

NMI = !( FF_NMI && !FF_ALLRAM )

RAM.CE = !( !FF_PAGE + !MREQ + !A14 + !A15 + A13 )
ROM.CE = !( !FF_PAGE + !MREQ + !A14 + !A15 + !A13 )


FF_PAGE.SET = !RESET
FF_PAGE.RES = !( !MREQ + !RD + !M1 + %0000.0000.01100110 + FF_NMI + !FF_ALLRAM )
FF_PAGE.CLK = !( !IORQ + !RD + %-011.1111 + (A7 | !FF_HIDE) )
			-> Din = A7

FF_NMI.SET = !( !FF_NMI + !Taster )
FF_NMI.RES = !RESET
FF_NMI.CLK = PAL.WPORT = !( !IORQ + !WR + %-011.1111 )
			-> Din = 0

FF_HIDE.SET = !RESET
FF_HIDE.RES = !( !FF_NMI + !Taster )
FF_HIDE.CLK = !( !IORQ + !WR + %0011.1111 )
			-> Din = 1

FF_ALLRAM.SET = -
FF_ALLRAM.CLR = !RESET
FF_ALLRAM.CLK = !( !IORQ + !WR + %0001.----.11111101 )
			-> Din = D0 --> Port $1FFD Bit0 = Paging mode: 1 = Ram only

4x4RAM.addr = A13,A14
4x4RAM.WR = !( !IORQ + !WR + %0--1.----.11111101 )
4x4RAM.RD = !( !IORQ + !RD + %-011.1111 + !FF_HIDE )