Newsgroups: comp.sys.sinclair
Path: vanilla!asbach!noris.net!blackbush.xlink.net!sol.ctr.columbia.edu!news.uoregon.edu!gatech2!usenet.eel.ufl.edu!warwick!spuddy!spuddy.mew.co.uk!arcsalt
From: arcsalt@spuddy.mew.co.uk (Darren Salt)
Subject: Re: 128K Spectrum Tech Info
Message-ID: <466D1FE1B2.DC90@spuddy.mew.co.uk>
Sender: arcsalt@spuddy.mew.co.uk (Darren Salt)
Reply-To: arcsalt@spuddy.mew.co.uk
Organization: Spud's Public Usenet Domain
X-Newsreader: Archimedes TTFN Version 0.36
References: <47j6it$2b1c@acs5.acs.ucalgary.ca>
Date: Wed, 8 Nov 1995 02:06:06 GMT
Lines: 92

In article <47j6it$2b1c@acs5.acs.ucalgary.ca>,
	sealbrec@acs.ucalgary.ca (Alvin Albrecht) wrote:

> Is there a comprehensive technical FAQ for the 128K Spectrums somewhere?
> I spent several hours looking for one, but with no luck.  Specifically,
> I'm looking for port assignments (and functional description) for the
> AY chip and details on how the extra memory was bankswitched and handled
> by the OS.

Don't know about any FAQ, but I have the following information, gathered from
the +3 manual:

Default memory map (top 16K is paged RAM)

0000	4000	8000	C000
ROM	Bank5	Bank2	Bank0

Bank 7 is paged in by the OS for editor / +3DOS use; the user doesn't get to
see this.

OUT	b5	b4	b3	b2	b1	b0

&1FFD	-	STROBE	Motor	ROM1/X1	X0	RAMX	+2A/+3 only
&7FFD	Lock	ROM0	Screen	RAM2	RAM1	RAM0	Any

&0FFD	Printer port data latch (w), BUSY (b0, r)
&2FFD	µPD765A FDC status register
&3FFD	FDC data register

&BFFD	Sound chip data (r/w)
&FFFD	Sound chip register (w)

Key:
STROBE	Parallel port strobe bit (active low)
Motor	Disk drive motor (set = on)
Lock	Lock to current configuration - can only be cleared by RESET
ROM1	Bit 1 of ROM bank number
ROM0	Bit 0 of ROM bank number
Screen	Screen select (bank 5 if clear, bank 7 if set)
RAMx	Bit x of RAM bank number [banks 4 to 7 are contended by the ULA]
RAMX	Extended memory paging (if set):
	X1	X0	RAM bank order
	0	0	0,1,2,3
	0	1	4,5,6,7
	1	0	4,5,6,3
	1	1	4,7,6,3

ROM banks:

	128	+2a/+3	ROM
		0	+3 editor/BASIC
		1	+3DOS
	0	2	Editor/BASIC
	1	3	Old ROM


Sound chip details:

Clock is 1.7734MHz

Channel Tone	Tone	Volume
	Low	High
1	R0	R1	R8		Low is 8 bit, high is 4 bit
2	R2	R3	R9		Volume is 5 bit; values >=16 mean
3	R4	R5	R10		use envelope generator instead

R6 = noise generator control (5 bit value)
R7 = mixer / IO control
	b7	b6	b5	b4	b3	b2	b1	b0
	-	I/O	Noise control bits...	Tone control bits...
		(1=I)	Ch3	Ch2	Ch1	Ch3	Ch2	Ch1

R11 = envelope period, high
R12 = envelope period, low	(together = 16-bit value)

R13 = envelope control
	b3		b2		b1		b0
	Continue	Attack		Alternate	Hold

	Graphic representation: (8-15 are similar, I think)
	0	1	2	3	4	5	6	7
			  __	 ___
	\___	/|__	\|	/	\|\|	/|/|	/\/	\/\


--
+--------------------------------------------------------------------------+
| Darren Salt -- arcsalt@spuddy.mew.co.uk -- Toon at the top! -- Acorn nut |
| Also known as darren.salt@unn.ac.uk on Tuesdays and Thursdays, term time |
+---01268-515441-for-free-email-&-Usenet-----now-awaiting-normal-service---+

Sooner or later, the worst possible set of circumstances is bound to occur.