CHROMA81 Switch 1: ON: enable 16K RAM at $4000-$7FFF. Switch 2: ON: enable WRX graphics support for the CHROMA RAM. (=> read pixels from charset in RAM) Switch 3: ON: enable 8K RAM at $2000-$3FFF. Switch 4: ON: enable QS Character Board emulation at $8400 and $C400-$C7FF. Switch 5: ON: enable RS232 socket. Switch 6: ON: enable 16K RAM at $C000-$FFFF and enable the colour modes. _________________________________________________ OUT $7FEF, %00EMIGRB: Select colour mode E = enable color M = color mode (s.u.) IGRB border color If configuration switch 6 is set to OFF, the colour mode is forcibly disabled, colour mode 0 (character code mapping) selected, and the border restored to bright white. _________________________________________________ IN $7FEF: only bit 6 is valid: 0 = color modes available (CHROMA present and config switch 6 = ON) _________________________________________________ color mode 0: 48K-49K holds a colour look-up table consisting of 128 characters (64+64inverted) each of 8 lines. => attr byte is at: $C000+(char*8)+line attr bytes: %IGRBigrb IGRB paper color igrb pen color _________________________________________________ color mode 1: attributes are read from DFILE | 0xC000. --> 48K-64K => DFILE can also be in range 8K++ and 32K++ but not below 8K! _________________________________________________ CHR$128 mode: When RAM is fitted to the internal data bus connected to the ZX81 ROM, then setting the I register to value between $20-$3F will cause the display mechanism to fetch character pixel patterns from the 8K-16K region. Normally, there would be 64 characters and then the hardware would automatically generate their inverse forms. CHR$128 mode extends this to allow the inverse characters to be separately defined. The pixel pattern lookup address is specified by the I register but only bits 1-7 are used, not bit 0. CHR$128 therefore notes bit 0 of the I register (which it can do during a Refresh when the IR registers are placed on the address bus). If bit 0 is 0 then the normal 64 character UDG mode is active. But if bit 0 is 1 then the extended 128 character UDG mode is active. In 64 character mode, 0.5K holds the pixel patterns. In 128 character mode, 1K is used to hold the pixel patterns. The first 0.5K holds the definitions for the non-inverted characters, and the second 0.5K holds the pixel patterns for the inverted characters. Bit 7 of the character code normally indicates if a character is to be inverted. It is noted by Chroma and used to access the first or second 0.5K of RAM point at by the I register. The display hardware will still use bit 7 of the character code to invert the pixel patterns, so the pixel patterns for the inverse characters need to be stored in RAM in inverted form and the display hardware then un-inverts them. For the standard lo-res display, the display hardware fetches the character code via an opcode fetch and then during the Refresh cycle of that opcode fetch, the pixel pattern corresponding to the character code is looked up from the ROM. During a Refresh, the IR registers are placed on the address bus. For CHR$128 mode, the I register (bits1-7) is combined with the 6-bit character code and the 3-bit line counter to form the look up address to read the pixel pattern from. For WRX mode, the IR registers are used to fetch the actual pixel pattern byte from RAM to display. So both are trying to return the pixel pattern byte to display but only one mode or the other can be active at a time to supply it. For Chroma-81, if WRX mode is enabled (via switch 2) then WRX mode applies to the 16K RAM and the 8K RAM at 8K-16K (if switch 3 is on). Chroma’s WRX switch 2 only affects the RAM provided by Chroma; if other RAM is provided by another interface then Chroma’s switch won’t make it WRX enabled. _________________________________________________ Sound: The video signal is output to the audio channels of the SCART socket whenever video synchronisation is lost. _________________________________________________ Rear expansion bus: the Chroma81 suppresses memory access behind itself. With a ROM cartridge plugged in, the /MREQ and /RFSH lines of the rear expansion bus is held high to prevent a device plugged in behind seeing ROM address accesses. _________________________________________________ Reset: A reset button is directly connected to /RST. resetting the CPLD takes somewhat longer than CPU reset. _________________________________________________ Cartridge socket: With a ROM cartridge plugged in, the /MREQ and /RFSH lines of the rear expansion bus is held high to prevent a device plugged in behind seeing ROM address accesses. The ROM cartridge socket also overrides the character bitmap generator inside the ZX81. A ROM cartridge can populate all of the ROM address space from $0000-$3FFF. A ROM cartridge will override the onboard 8K RAM at $2000 and $A000 if it is enabled. NIMP: Early ZX81 ROMS had a bug in the FP math. One fix was to add a HW which forced some bits at certain addresses. _________________________________________________ Joystick socket: The joystick socket supports the cursor format. The socket is read using two input ports: $F7FE and $EFFE. The data matches keyboard key 5..8 + 0. _________________________________________________ RS232 Socket: Handshake: For a PC, the RTS line should be used, whereas for a serial printer the DTR line should be used. A JUMPER is present on the Chroma interface to select which handshaking line to receive. The RS232 socket is enabled using configuration switch 5. The RS232 socket is controlled by I/O port $FEEF. The address lines are fully decoded. The data is sent and received INVERTED. (--> CPL) Upon resetting the ZX81 or disabling of the RS232 socket via switch 5, the output lines are set to the IDLE state. OUT $FEEF, %000000HD H = handshake: 1=ok to send D = data, inverted, 0=idle %DHxxxxx0 = IN $FEEF D = data, inverted, 0=idle H = handshake, 1=ok to send 0 = RS232 port present & enabled _________________________________________________ RAM: The CHROMA81 has 32K of Ram. Any enabled RAM will prevent a device plugged in behind seeing RAM address accesses. 16K can be enabled at 16-32K 'onboard ram'. 16K appear at 3 locations: $C000 16K: color attributes at DFILE | $C000 (mode 1) $C000 1K: color map (mode 0) $C400 1K: QS char board, visible at $8400 and $C400 $E000 8K: at $2000, $A000 and $E000 Switch3: enable 8K at $2000 and $A000 Switch6: enable 16K at $8000 => 8K also visible at $E000