Release Notes for STM32H7xx CMSIS

Copyright © 2017 STMicroelectronics

License

This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
https://opensource.org/licenses/BSD-3-Clause

Update History

Main Changes

  • Add support of stm32h723xx, stm32h725xx, stm32h733xx, stm32h735xx, stm32h730xx and stm32h730xxQ devices:
    • Add “stm32h723xx.h” , “stm32h725xx.h”, “stm32h733xx.h”, “stm32h735xx.h”, “stm32h730xx.h” and “stm32h730xxq.h” files
    • Add startup files “startup_stm32h723xx.s”, “startup_stm32h725xx.s”, “startup_stm32h733xx.s”, “startup_stm32h735xx.s”, “startup_stm32h730xx.s” and “startup_stm32h730xxq.s” for EWARM , MDK-ARM and GCC toolchains
    • Add part numbers list to stm32h7xx.h header file:
      • STM32H723xx: STM32H723VGH6, STM32H723VGT6, STM32H723ZGI6, STM32H723ZGT6, STM32H723VET6, STM32H723VEH6, STM32H723ZET6, STM32H723ZEI6 Devices
      • STM32H725xx: STM32H725AGI6, STM32H725IGK6, STM32H725IGT6, STM32H725RGV6, STM32H725VGT6, STM32H725VGY6, STM32H725ZGT6, STM32H725REV6, SM32H725VET6, STM32H725ZET6, STM32H725AEI6, STM32H725IET6, STM32H725IEK6 Devices
      • STM32H733xx: STM32H733VGH6, STM32H733VGT6, STM32H733ZGI6, STM32H733ZGT6, Devices
      • STM32H735xx: STM32H735AGI6, STM32H735IGK6, STM32H735RGV6, STM32H735VGT6, STM32H735VGY6, STM32H735ZGT6 Devices
      • STM32H730xx: STM32H730VBH6, STM32H730VBT6, STM32H730ZBT6, STM32H730ZBI6 Devices

      • STM32H730xxQ: STM32H730IBT6Q, STM32H730ABI6Q, STM32H730IBK6Q Devices

      • Add EWARM STM32H723xx, STM32H725xx, STM32H733xx, STM32H735xx, STM32H730xx and STM32H730xxQ devices linker files (1MB flash) for EWARM toolchain

      • Add EWARM STM32H723xE and STM32H725xE devices linker files (Subset 512KB flash) for EWARM toolchain

    • Note : stm32h730xx and stm32h730xxQ are Value line devices with 128KB flash:
  • Update STM32H7 devices header files:
    • Fix FDCAN_ECR_TEC_Msk definition (8 bits bit field instead of 4)
    • Fix IS_SMBUS_INSTANCE macro definition with the right instances list for each STM32H7 line
  • Update system_stm32h7xx.c, system_stm32h7xx_dualcore_boot_cm4_cm7.c, system_stm32h7xx_dualcore_bootcm4_cm7gated.c, system_stm32h7xx_dualcore_bootcm7_cm4gated.c and system_stm32h7xx_singlecore.c files to:
    • Add Flash latency settings depending of the previous CPU frequency (Increasing or decreasing the CPU frequency)
    • Fix RCC registers reset values settings
    • Disable the FMC bank1 (enabled after reset)
      • This prevents CPU speculation access on this bank which blocks the use of FMC during 24us. During this time the others FMC master (such as LTDC) cannot use it
  • Update system_stm32h7xx.c, system_stm32h7xx_dualcore_boot_cm4_cm7.c, system_stm32h7xx_dualcore_bootcm4_cm7gated.c and system_stm32h7xx_dualcore_bootcm7_cm4gated.c to:
    • Use D2_AXISRAM_BASE for Coretx-M4 VTOR when executing from RAM instead of D2_AHBSRAM_BASE
      • Note: both addresses are aliases to the same D2 domain physical RAM. D2_AXISRAM_BASE (@0x10000000) gives access to the RAM with access using Instruction bus (I), where D2_AHBSRAM_BASE(@0x30000000) gives access to the RAM with access using Data bus. thus when executing from this D2 RAM it is recommended to use D2_AXISRAM_BASE alias so the execution scheme respects the Harvard architecture (One bus for data and one bus for instructions).
  • Update system_stm32h7xx.c and system_stm32h7xx_dualcore_boot_cm4_cm7.c to:
    • Fix usage of SCB->SCR register: SEVONPEND enabled so that an interrupt generated by the other CPU triggers an event and wakes up the current CPU after a WFI/WFE instruction even if the interrupt is disabled
  • Add EWARM, linker files for STM32H742xG and STM32H743xG devices coming with 1MB flash: 512KB for each bank

  • Add EWARM, MDK-ARM and GCC linker files for STM32H745xG and STM32H747xG devices coming with 1MB flash: 512KB for each bank

  • Update GCC startup files for all devices to align sequence to EWARM/MDK-ARM by calling “SystemInit” prior to any memory access
    • Allowing to avoid issues when using external memories

Main Changes

  • General updates to align Bits and registers definitions with the STM32H7 reference manual
  • Update “ErrorStatus” enumeration definition in stm32h7xx.h file with SUCCESS set to numerical value zero
  • Add definition of DMA_SxCR_TRBUFF bit field of DMA SxCR register allowing to enabled/disable bufferable transfers
  • Remove RCC_AHB2ENR_CRYPEN/RCC_AHB2RSTR_CRYPRST/RCC_AHB2LPENR_CRYPLPEN and RCC_AHB2ENR_HASHEN/RCC_AHB2RSTR_HASHRST/RCC_AHB2LPENR_HASHLPEN from H7 devices that doesn’t support CRYP/HASH (STM32H742/43/45/47/A3)
  • Add STM32H7_DEV_ID define allowing to identify the H7 Device ID
  • Update OCTOSPIM_TypeDef structure definition with 3 PCR registers instead of 8 (on STM32H7A3/B3/B0 devices supporting OctoSPI)
  • Add definition for OCTOSPIM_CR_MUXEN and OCTOSPIM_CR_REQ2ACK_TIME in order to support OctoSPI IO Manager multiplexed mode feature (on STM32H7A3/B3/B0 devices supporting OctoSPI)
  • Update system_stm32h7xx.c to reflect the current core clock in SystemCoreClock global variable (Corex-M7 or Corext-M4 clock depending of the current context in case of Dual Core)
  • Add EWARM linker files for STM32H7A3 devices with reduced Flash size to 1MB:
    • stm32h7a3xg_flash.icf, stm32h7a3xg_flash_rw_sram1.icf, stm32h7a3xg_flash_rw_sram2.icf.
    • stm32h7a3xgq_flash.icf, stm32h7a3xgq_flash_rw_sram1.icf, stm32h7a3xgq_flash_rw_sram2.icf.

Main Changes

  • General updates to align Bit and registers definition with the STM32H7 reference manual

  • Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices:
    • Add “stm32h7a3xx.h”, “stm32h7a3xxq.h”, “stm32h7b3xx.h”, “stm32h7b3xxq.h”, “stm32h7b0xx.h” and “stm32h7b0xxq.h” files
    • Add startup files “startup_stm32h7a3xx.s”, “startup_stm32h7a3xxq.s”, “startup_stm32h7b3xx.s”, “startup_stm32h7b3xxq.s”, “startup_stm32h7b0xx.s” and “startup_stm32h7b0xxq.s” for EWARM , MDK-ARM and STM32CubeIDE toolchains
    • Add part numbers list to stm32h7xx.h header file:
      • STM32H7A3xx : STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6
      • STM32H7A3xxQ : STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q
      • STM32H7B3xx : STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6
      • STM32H7B3xxQ : STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q
      • STM32H7B0xx : STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ
  • Update DMA2D bits definitions: Update to support Line offset mode and swap bytes features
    • Add CR_LOM (Line Ofset Mode) bit definition, Add OPFCCR_SB (Swap Bytes) bit definition
    • Update CR_MODE, FGOR_LO, BGOR_LO and OOR_LO bit definition
  • Update USB_OTG_GAHBCFG bit definition: to be aligned with LL_USB usage

  • Add USB_OTG_DOEPMSK_AHBERRM, USB_OTG_DOEPMSK_BERRM, USB_OTG_DOEPMSK_NAKM, USB_OTG_DOEPMSK_NYETM, USB_OTG_DIEPINT_AHBERR, USB_OTG_DIEPINT_INEPNM, USB_OTG_DOEPINT_AHBERR, USB_OTG_DOEPINT_OUTPKTERR, USB_OTG_DOEPINT_BERR, USB_OTG_DOEPINT_NAK and USB_OTG_DOEPINT_STPKTRX bit definitions

  • Update IS_TIM_REMAP_INSTANCE and IS_TIM_SYNCHRO_INSTANCE macro implemenation

Main Changes

  • Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices
  • Add definition of “ART” instance: pointer to “ART_TypeDef” structure
  • Add definition of “ART” bit fields: ART_CTR_EN and ART_CTR_PCACHEADDR
  • Update definitions of “HRTIM1_TIMA” to “HRTIM1_TIME” : pointer to HRTIM_Timerx_TypeDef structure instead of HRTIM_TIM_TypeDef
  • Fix Typo in “ETH_TypeDef” definition: use uint32_t for “RESERVED16” registers instead of int32_t
  • Remove useless definition of “SDMMC” instance (keep only definitions of “SDMMC1” and “SDMMC2”)

Main Changes

  • General updates to align Bit and registers definition with the STM32H7 reference manual
  • Updates to aligned with STM32H7xx rev.V devices
  • Add support of stm32h745xx, stm32h747xx, stm32h755xx, stm32h757xx Dual Core devices and STM32H742xx (new single core device):
    • Add “stm32h745xx.h” , “stm32h747xx.h”, “stm32h755xx.h”, “stm32h757xx.h” and “stm32h742xx.h” files
    • Add startup files “startup_stm32h745xx.s”, “startup_stm32h747xx.s”, “startup_stm32h755xx.s”, “startup_stm32h757xx.s” and “startup_stm32h742xx.s” for EWARM , MDK-ARM and SW4STM32 toolchains
    • Add part numbers list to stm32h7xx.h header file:
      • STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI
      • STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI
      • STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI
      • STM32H750xx: STM32H750V, STM32H750I, STM32H750X
      • STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI
      • STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI
      • STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI

      • STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI

      • Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)
      • Add system initialization template source file for dual core lines:
        • system_stm32h7xx_dualcore_boot_cm4_cm7.c: template for the boot case where Cortex-M7 and Cortex-M4 are boot at once
        • system_stm32h7xx_dualcore_bootcm7_cm4gated.c: template for the boot case where Cortex-M7 is booting and Cortex-M4 is gated using FLASH Option Bytes
        • system_stm32h7xx_dualcore_bootcm4_cm7gated.c: template for the boot case where Cortex-M4 is booting and Cortex-M7 is gated using FLASH Option Bytes
      • Add EWARM, MDK-ARM and SW4STM32 Dual Core devices linker files

      • Add EWARM STM32H742xx devices linker files

  • Registers and bit field definitions updates:
    • Update SYSCFG_TypeDef structure to add
      • Add CFGR register: allowing to control connection between double ECC RAMs/Flash errors, PVD errors and CortexM7/M4 lockup to TIM1/8/15/16/17 and HRTIMER Break inputs
      • Add definitions of SYSCFG_CFGR register bit fields
      • PWRCR registers: allowing to control the PWR overdrive enable/disable for Voltage Scaling zero
      • Add SYSCFG_PWRCR register bit fields
    • Update RCC_TypeDef structure according to STM32H7xx Rev.V devices:
      • ICSCR: renamed to HSICFGR, HSI Clock Calibration Register
      • Rename also RCC_ICSCR_XXX bit definitions RCC_HSICFGR_XXX according to the new register HSICFGR
      • CSICFGR: New registers (on Rev.V devices), CSI Clock Calibration Register
      • Add dedicated RCC_CSICFGR_XXX bit definitions
    • Keep RCC_Core_TypeDef structure used for Dual Core lines devices only: allowing RCC clock enabling/allocation for each Core(Cortex-M7/M4)
      • RCC_Core_TypeDef structure and RCC_C1_BASE/RCC_C1 definition removed from STM32H743xx/53xx and STM32H750xx lines
    • Add CRYP_CR_NPBLB bit field definition: upon refresh of the CRYP peripheral on the STM32H7 Rev.V devices
    • Update ADC_CR_BOOST bot field definition for STM32H7 Rev.V devices: 2 bits instead of 1
    • Remove useless I2C_CR1_SWRST definition: alignment with the reference manual
    • Add SAI_xCR1_NODIV bit field definition upon SAI peripheral update for STM32H7 Rev.V devices
    • Rename SPI_TXCRC_RXCRC to SPI_RXCRC_RXCRC: typo fix and alignment with the reference manual
    • Fix QUADSPI_SR_FLEVEL bit field definition: Mask on 6 bits (0x3F mask) instead of 5 bits(0x1F mask) and add definition of QUADSPI_SR_FLEVEL_6
    • Add definition of SYSCFG_EXTICR3_EXTI8_PK, SYSCFG_EXTICR3_EXTI9_PK, SYSCFG_EXTICR3_EXTI10_PK, SYSCFG_EXTICR3_EXTI11_PK and SYSCFG_EXTICR4_EXTI13_PK
    • Add definition of FLASH_LATENCY_DEFAULT: default safe FLASH latency

Main Changes

  • Patch Release on top of V1.3.0
  • Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
    • stm32h743xx.h, stm32h750xx.h and stm32h753xx.h

Main Changes

  • STM32H7xx include files:
    • General updates to align Bit and registers definition with the STM32H7 reference manual
    • Update "_Mask" bits definition using UL suffix for Misra-C 2012 compliance
    • Add definition of RAMECC_MonitorTypeDef and RAMECC_TypeDef structure
    • Add definition of RAMECC peripheral base addresses
    • Add RAMECC peripheral registers bit definitions
    • Add IS_RAMECC_MONITOR_ALL_INSTANCE macro
    • Add EXTI SWIER3 bit definitions
    • Update FLASH sector number to 8 instead of 16 (8 sectors for each bank)
    • Remove extra bit definition : FLASH_CR_SNB_3 to FLASH_CR_SNB_7
    • Update FLASH user option bytes bit definition
    • Fix FLASH_BANK_SIZE definition: add parenthesis
    • Remove PWR extra bit definition PWR_CR1_RLPSN
    • Add PWR bit definition PWR_WKUPEPR_WKUPEN
    • Fix typo in SDMMC bit definition: SDMMC_MASK_SDIOITIE_Pos, SDMMC_MASK_SDIOITIE_Msk and SDMMC_MASK_SDIOITIE
    • Add SDMMC instance check macro: IS_SDMMC_ALL_INSTANCE
    • Fix typo in SYSCFG bit definition: SYSCFG_PMCR_EPIS_SEL_Pos, SYSCFG_PMCR_EPIS_SEL_Msk, SYSCFG_PMCR_EPIS_SEL and SYSCFG_PMCR_EPIS_SEL_0 to SYSCFG_PMCR_EPIS_SEL_2
    • Fix SYSCFG bit definitions: SYSCFG_EXTICR1_EXTI0_Msk, to SYSCFG_EXTICR1_EXTI3_Msk, 4 bits instead of 3
    • Fix SYSCFG bit definitions: SYSCFG_EXTICR2_EXTI0_Msk, to SYSCFG_EXTICR2_EXTI3_Msk, 4 bits instead of 3
    • Fix SYSCFG bit definitions: SYSCFG_EXTICR3_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI3_Msk, 4 bits instead of 3
    • Fix SYSCFG bit definitions: SYSCFG_EXTICR4_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI4_Msk, 4 bits instead of 3
    • Fix IS_ADC_COMMON_INSTANCE macro : add parenthesis
    • Fix HSEM_CR_COREID_CURRENT and HSEM_CR_COREID_CURRENT: add parenthesis
    • Update USART and SMARTCARD bits definition
    • Update GPIO registers and bit definition (BSRR register)
    • Add IS_GPIO_AF_INSTANCE macro
    • Update DAC bits definition
    • Update FDCAN bits definition
    • Update USB bits definition (OTEPSPRM register)
    • Fix CEC bit definition (RXDR register)
    • Update TIM registers and bits definition naming
    • Fix IS_TIM_CCX_INSTANCE macro : add TIM_CHANNEL_4 to TIM_CHANNEL_6
    • Update SPI and I2S bits definition
    • Update BDMA bits definition
    • Update FMC bits definition

Main Changes

  • Add support for stm32h750xx value line devices:
    • Add “stm32h750xx.h” file
    • Add startup files startup_stm32h750xx.s for EWARM, MDK-ARM and SW4STM32

Main Changes

  • Update FDCAN bit definition
  • Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access

Main Changes

  • Update USB OTG bit definition
  • Adjust PLL fractional computation

Main Changes

  • First official release for STM32H743xx/753xx devices