Video Display Emulation of a [virtual] graphical video display –––––––––––––––––––––––––––––––––––––––––––––––– Goal: • The emulation should implement hardware which could really be built. • Graphical color terminal • Multiple resolutions to play with • Memory mapped video ram for fast access Video Ram: The video ram is memory mapped. For fast access the video ram is organized in planes: Each plane contains one bit of all pixels. Drawing goes to all planes in one go. Implementation of only one plane results in a monochrome display. Color Ram: True Color is easier to implement, but needs more planes for a colorful image. Indexed Color allows flashing of colors and colorful image with only few planes, or logical planes. Indexed color requires an additional color ram. This color look-up table may be also mapped into the CPU memory address space. It uses 2 bytes per entry and has up to 256 entries for 8 video ram planes. 2 Drawing Modes: When writing to the videoram, data is written to all planes simultaneously. So if the CPU writes one byte, 8 pixels are affected. Transparent Drawing Mode: First, a 'color' is written to the Color Index Register. Then, when writing to the video ram only the '1' bits are actually modified and set to the selected color, which means they are set to '0' or '1' as stored in the 'color index' bit of their plane. '0' bits written are preserve the respective bit in all planes. This way the CPU can set up to 8 pixels to a new color while preserving the background pixels in a single write instruction. This mode is ideal for printing text and sprites with only few colors. It is not ideal but good for drawing points and lines. Direct Drawing Mode: First, a 'plane mask' is written to the Color Index Register. Then when writing to the video ram, the byte written is only stored in the planes which have their bit set in the plane mask. This mode is good in monochrome mode with only one plane and for drawing images and sprites with many colors. 4 Display Modes: Display modes vary in video ram plane size and pixel clock frequency. Display Mode 0: 8 kB videoram and 6.25 MHz pixel clock, e.g. 320 x 200 pixels or 40 x 25 characters. This mode can be used to generate a 50Hz or 60Hz non-interlaced TV image. Display Mode 1: 16 kB videoram and 12.5 MHz pixel clock, e.g. 640 x 200 pixels or 80 x 25 characters. This mode can be used to generate a 50Hz or 60Hz non-interlaced TV image. Display Mode 2: 32 kB videoram and 25 MHz pixel clock, e.g. 640 x 400 pixels or 80 x 50 characters. This mode can be used to generate a VESA 640x480x60Hz monitor image. Display Mode 3: 64 kB videoram and 40 MHz pixel clock, e.g. 800 x 600 pixels or 100 x 75 characters. This mode can be used to generate a VESA 800x600x60Hz monitor image. Interrupt: An interrupt is generated at the start of a frame. A frame starts with the VSync signal. TODO: eventually at the first line of the lower border. The interrupt is removed by reading register 0 (Video Mode Register). Registers: Registers can only be written to, not read. I/O Registers [/CS1] Register 0: Video Mode Register Register 1: Color Index Register Register 2,3: Screen Start Address Potentially Memory Mapped Registers [/CS2] Registers $000 …: 256x2 bytes Color Look-up Table Registers $200 …: hsync, blanking+border, screen, border+blanking vsync, blanking+border, screen, border+blanking DETAILED DESCRIPTION –––––––––––––––––––– I/O Registers [/CS1] Register 0: Video Mode Register Bits 0+1: Display Mode 0 … 3 Defines the page size (8kB … 64kB) and pixel clock (25/4, 25/2, 25, 40MHz) Bit 2: Alternate Clock Source Use 20MHz (40÷2) instead of the default clock source (25 or 40MHz) for this mode. This results in wider pixels and allows the available video ram to cover the whole visible screen (full width and all scan lines) in modes 0 to 2. In mode 3, which already covers the full screen, this allows to use only half of video ram for faster drawing. Bit 3: reserved, set to 0 Bit 4: Drawing Mode 0 = Transparent Drawing Mode (see description above) 1 = Direct Drawing Mode (see description above) Bits 5-7: HSync Fine Delay All horizontal timings are expressed in 'bytes' (pixel octets). Therefore the screen cannot be positioned pixel-precisely horizontally. This can be done by programming a value of 0 to 7 into bits 5 to 7 of this register. The HSync signal is delayed by this amount of pixels, moving the display left. Register 1: Color Index Register In Transparent Drawing Mode this register defines the color index to draw with. In Opaque Drawing Mode this defines the planes which are affected by writing to the video ram. See description above. Register 2, 3: Screen Start Address These registers define the reload value for the video ram address counters at the beginning of a frame. By reprogramming this register, horizontal and vertical scrolling of the screen can be achieved in hardware. Horizontal scrolling can only be programmed in byte increments. Potentially Memory Mapped Registers [/CS2] These values are store in a small 16 bit ram (two 8 bit rams) so that the 16 bit color words can be accessed simultaneously by the hardware. Color Loop-up Table: Register $000 … $1FF: The Color Look-up Table may be written to using memory-mapped addressing. The table consists of 256 2-byte entries for up to 256 colors in up to 8 planes. The bits in each word define red, green and blue as follows: %0rrrrrgg.gggbbbbb The low byte is stored first (on the even address). Horizontal Timing: Register $200: HSync Duration (bytes) Register $202: Blanking + Border (right porch + left border) Register $204: Screen Width Register $206: Border + Blanking (right border + front porch) Vertical Timing: Register $201: VSync Duration (lines) Register $203: Blanking + Border (right porch + top border) Register $205: Screen Height (low byte) Register $207: Border + Blanking (bottom border + front porch) All horizontal timing values are expressed in bytes (pixel octets). Only black border is supported to simplify handling of blanking and border. All vertical timings are expressed in scanlines. The Screen Height in Mode 2 has an implicit ninth bit and in Mode 3 an implicit tenth bit set to '1'. BASICS ON TV AND VIDEO SIGNALS –––––––––––––––––––––––––––––– Frames are made out of scanlines. A scan line consists of: short blanking (front porch) hsync pulse longer blanking (back porch) left border screen right border The front porch allows the analog circuitry to reach defined levels, so that the sync pulse triggers the circuit without timing jitter. The back porch also helps preventing jitter and allows the analog circuitry to settle. A video frame consists of: blank lines (front porch) special blank lines (vsync) blank lines (back porch) top border screen lines bottom border The front porch allows the analog circuitry to reach defined levels, so that the sync pulse triggers the circuit without timing jitter. The back porch also helps preventing jitter and allows the analog circuitry to settle. While VGA / Monitors have separate lines for the sync signals, the sync signal is encoded into the signal on a TV: (F)BAS signal levels @ 75Ω: HSync: 0.0V Black: 0.3V (PAL: blank: 0.285V, black: 0.339V) White: 1.0V The VSync signal is encoded as some blank lines with inverted voltage levels: HSync: 0.3V Blank: 0.0V TV "frames" are "interlaced" from two "fields" to double the vertical resolution. PAL: 50Hz with 625 lines. NTSC: 60Hz with 525 lines. For interlaced video, the porches and sync pulse consist of half lines. PAL TV: frame rate: 50 Hz = 20ms/frame lines / frame: 312.5 hor. freq.: 50 * 312.5 = 15625 Hz hor: total = 64.0µs front porch = 1.65µs hsync = 4.7µs back porch = 5.7µs visible screen = 51.95µs vert: total = 312.5 lines front porch = 3.0 / 2.5 (field 1 / field 2) vsync = 2.5 / 2.5 back porch = 2.5 / 2.0 invisible lines = 18 visible screen = 286 invisible lines = 0.5 / 1.5 NTSC TV: frame rate: 60 Hz = 16.7ms/frame lines / frame: 262.5 hor. freq.: 60 * 262.5 = 15750 Hz hor: total = 63.5µs front porch = 1.4µs hsync = 4.7µs back porch = 5.9µs visible screen = 51.5µs vert: total = 262.5 lines front porch = 3.0 / 3.5 (field 1 / field 2) vsync = 3.0 / 3.0 back porch = 3.0 / 2.5 invisible lines = 10 visible screen = 242 invisible lines = 1.5 DISPLAY MODES ––––––––––––– Pixel clock: Ideal pixel clock for square pixels on a TV at 50Hz is ~7MHz and for 60Hz it is ~6Mhz. We need 25.175MHz for Display Mode 2 (VESA 640x480x60Hz). We need 40.000MHz for Display Mode 3 (VESA 800x600x60Hz). The standard clocks for Mode 0 and 1 (TV) are derived from 25MHz with 2:1 dividers: => Mode 0: 6.29375 MHz. 0.159 µs / pixel 1.27 µs / octet (char) Mode 1: 12.5875 MHz. The 'alternate' clock for all Display Modes is derived from 20MHz, so it is 5MHz in Mode 0, 10MHz in Mode 1 and 20MHz in Mode 2 and 3. Mode 0: 320 x 200 Pixel, 8 kB / plane 40 x 25 Characters. (or 38x26 or 36x28) For games on TV. Requires 8kB write address space in system memory. Actually we cannot display 320 pixels because the side borders will be too narrow. Using 304x208 (38x26char) or 288x224 (36x28char) is recommended. Timing: (50Hz) lines / frame: 312 pixel clock: 6.29375MHz pixel / line: 6293750 / 50 / 312 = 403.45 pixel pixel / line: 400 pixel = 50 x 8 (sync to sync) frame rate: 1/(312*400/6.29375MHz) = 50.43Hz hor: total = 50 char (400 pixel, sync to sync) hsync = 4 blank = 5 (back porch + left border) screen = 40 (40 char = 50.85µs, visible (PAL) = 51.95µs!) blank = 1 (right border + front porch) vert: total = 312 lines vsync = 4 blank = 64 (back porch + upper border) screen = 200 blank = 44 (lower border + front porch) Timing: (60Hz) lines / frame: 262 pixel clock: 6.29375MHz pixel / line: 6293750 / 60 / 262 = 400.37 pixel pixel / line: 400 pixel = 50 x 8 (sync to sync) frame rate: 1/(262*400/6.29375MHz) = 60.055Hz hor: same as 50Hz total = 50 char (400 pixel, sync to sync) hsync = 4 blank = 5 (back porch + left border) screen = 40 (40 char = 50.85µs, visible (NTSC) = 51.5µs!) blank = 1 (right border + front porch) vert: total = 262 lines vsync = 4 blank = 36 (back porch + upper border) screen = 200 blank = 22 (lower border + front porch) Alternate Timing: (50Hz) 32 x 32 Characters lines / frame: 312 pixel clock: 5.000MHz pixel / line: 5MHz / 50Hz / 312 = 320.5 pixel pixel / line: 320 pixel = 40 x 8 (sync to sync) frame rate: 1/(312*320/5e6) = 50.08Hz hor: total = 40 char (320 pixel, sync to sync) hsync = 3 (4.8µs) blank = 4 (6.4µs: back porch + left border) screen = 32 (51.2µs: visible (PAL) = 51.95µs) blank = 1 (1.6µs: right border + front porch) vert: total = 312 lines vsync = 4 blank = 36 (back porch + upper border) screen = 256 (32 character rows) blank = 16 (lower border + front porch) Alternate Timing: (60Hz) 32 x 28 Characters lines / frame: 262 pixel clock: 5.000MHz pixel / line: 5MHz / 60Hz / 262 = 318.1 pixel pixel / line: 320 pixel = 40 x 8 (sync to sync) frame rate: 1/(262*320/5e6) = 59.64Hz hor: same as 50Hz total = 40 char (320 pixel, sync to sync) hsync = 3 (4.8µs) blank = 4 (6.4µs: back porch + left border) screen = 32 (51.2µs: visible (NTSC) = 51.5µs!) blank = 1 (1.6µs: right border + front porch) vert: total = 262 lines vsync = 4 blank = 24 (back porch + upper border) screen = 224 (28 character rows) blank = 10 (lower border + front porch) Mode 1: 640 x 200 Pixel, 16 kB / plane 80 x 25 Characters. (or 76x26 or 72x28) For display of text on TV with SCART. Requires 16kB write address space in system memory. Timing is identical to mode 0, except that the pixel clock and therefore all values expressed in pixels or chars are doubled. Mode 2: 640 x 400 Pixel, 32kB / plane 80 x 50 Characters. For use with a monitor. Requires 32kB write address space in system memory. Timing: VESA 640x480@60Hz pixel clock: = 25.175MHz pixel / line: = 800 lines / frame: = 525 = 31.8µs frame rate: = 60Hz = 16.7ms sync polarity: = negative HSync, negative VSync hor: total = 100 char (800 pixel, sync to sync) hsync = 12 blank = 6 (back porch + left border) screen = 80 blank = 2 (right border + front porch) vert: total = 525 lines vsync = 2 blank = 33 (73) (back porch + upper border) screen = 480 (400) (video ram too small for 480 lines) blank = 10 (50) (lower border + front porch) Mode 3: 800 x 600 Pixel, 64kB / plane 100 x 75 Characters. For use with a monitor. Requires 64kB write address space in system memory => circuitry for segmentation required! Timing: VESA 800x600@60Hz pixel clock = 40.0MHz pixel / line = 1056 = 132 * 8 lines / frame = 628 = 26.4µs frame rate = 60.3Hz = 16.6ms sync polarity: = positive HSync, positive VSync hor: total = 132 char (1056 pixel sync to sync) hsync = 16 blank = 11 (back porch) screen = 100 blank = 5 (front porch) vert: total = 628 lines vsync = 4 blank = 32 (back porch) screen = 600 blank = 1 (front porch)