/*	Copyright  (c)	Günter Woigk 2012 - 2017
					mailto:kio@little-bat.de

	This file is free software
	License: see file "sio.cc"


	Dual UART 88C192 Driver for K1-Bus Board
	----------------------------------------

	This is the driver for a dual-sio board for the K1-Bus.
	For K1-Bus see: https://k1.spdns.de/Develop/Hardware/K1-Computer/IO-Boards/SIO/


	UART Port Connections:
	----------------------

	OP0	RTSA	or	Inverter Control for CLKA.out	(normally asserted (low) -> not inverted)
	OP1	RTSB	or	Inverter Control for CLKB.out	(normally asserted (low) -> not inverted)
	OP2	CLKA	or	Inverter Control for RTSA 		(should be asserted (low) -> not inverted)
	OP3	CLKB	or	Inverter Control for RTSB 		(should be asserted (low) -> not inverted)
	OP4	CTLA 		pin header
	OP5	CTLB		pin header
	OP6	CLKA.in.INV	Inverter Control for CLKA.in und CTSA  (normally asserted (low) -> not inverted)
	OP7	CLKB.in.INV	Inverter Control for CLKB.in und CTSB  (normally asserted (low) -> not inverted)

	IP0	CTSA	from HSKA
	IP1	CTSB	from HSKB
	IP2	+5V
	IP3	TXACLK	from HSKA
	IP4	RXACLK	from HSKA
	IP5	TXBCLK	from HSKB
	IP6	RXBCLK	from HSKB
*/


// UART clock:
#define XTAL	7372000

extern const
	uint8

// UART READ registers:
	MR0A = 0, 	// Mode Registers A
	MR1A = 0,
	MR2A = 0,
	SRA	 = 1,	// Status Register A
	UNUSED1,	//
	RXA	 = 3,	// Receive Buffer A
	IPCR = 4,	// Input Port Change Register
	ISR	 = 5,	// Interrupt Status Register
	CUR	 = 6,	// Counter/Timer Upper Register
	CLR	 = 7,	// Counter/Timer Lower Register
	MR0B = 8,	// Mode Registers B
	MR1B = 8,
	MR2B = 8,
	SRB	 = 9,	// Status Register B
	UNUSED2,	//
	RXB	 = 11,	// Receive Buffer B
	GPR	 = 12,	// General Purpose Register
	IPR	 = 13,	// Input Port Register
	STCR = 14,	// Start C/T Command
	SPCR = 15,	// Stop C/T Command

// UART WRITE registers:
	MR0A = 0,	// Mode Registers A
	CSRA = 1,	// Clock Select Register A
	CRA	 = 2,	// Command Register A
	TXA	 = 3,	// Transmitter Buffer A
	ACR	 = 4,	// Auxiliary Control Register
	IMR	 = 5,	// Interrupt Mask Register
	CTPU = 6,	// C/T Preload Value Upper Register
	CTPL = 7,	// C/T Preload Value Lower Register
	MR0B = 8,	// Mode Registers B
	CSRB = 9,	// Clock Select Register B
	CRB	 = 10,	// Command Register B
	TXB	 = 11,	// Transmitter Buffer B
	GPR	 = 12,	// General Purpose Register
	OPCR = 13,	// Output Port Configuration Register
	SOPR = 14,	// Set Output Port Register
	ROPR = 15,	// Reset Output Port Register

// Bits in misc. UART registers:

// bits in status register SRA & SRB:
	mSR_RX_ready	= 1,
	mSR_RX_full		= 2,
	mSR_TX_ready 	= 4,
	mSR_TX_empty 	= 8,
	mSR_RX_overrun	= 16,
	mSR_RX_parity	= 32,
	mSR_RX_framing	= 64,
	mSR_RX_break	= 128,
	bSR_RX_ready	= 0,
	bSR_TX_ready 	= 2,
	bSR_TX_empty	= 3,

// bits in interrupt mask register IMR and interrupt status register ISR
	mIMR_TXA_ready 	= 1,
	mIMR_RXA_ready	= 2,
	mIMR_RXA_break	= 4,
	mIMR_CT_ready	= 8,
	mIMR_TXB_ready	= 16,
	mIMR_RXB_ready	= 32,
	mIMR_RXB_break	= 64,
	mIMR_IP_changed	= 128,

// bits in SOPR, ROPR:
	mOPR_RTSA	= 1,	// RTSA	or	Inverter Control for CLKA.out	(normally asserted (low) -> not inverted)
	mOPR_RTSB	= 2,	// RTSB	or	Inverter Control for CLKB.out	(normally asserted (low) -> not inverted)
	mOPR_CLKA	= 4,	// CLKA	or	Inverter Control for RTSA 		(should be asserted (low) -> not inverted)
	mOPR_CLKB	= 8,	// CLKB	or	Inverter Control for RTSB 		(should be asserted (low) -> not inverted)
	mOPR_CTLA	= 16,	// pin header
	mOPR_CTLB	= 32,	// pin header
	mOPR_INVA	= 64,	// CLKA.in.INV	Inverter Control for CLKA.in und CTSA  (normally asserted (low) -> not inverted)
	mOPR_INVB	= 128,	// CLKB.in.INV	Inverter Control for CLKB.in und CTSB  (normally asserted (low) -> not inverted)


// Setup values for config registers:

// Output Port Configuration Register OPCR:
	OPCR_value
		= 0b00<<0			// OP2/CLKA = normal port mode
		+ 0b00<<2			// OP3/CLKB = normal port mode
		+ 0b0000<<4,		// OP4,5,6,7 = normal port mode

// Output Port Value: SOPR und ROPR:
	SOPR_value
		= mOPR_RTSA			// assert RTSA (just in case)
		+ mOPR_RTSB			// assert RTSB (just in case)
		+ mOPR_CLKA 		// Inverter Control for RTSA: asserted = 0 = don't invert
		+ mOPR_CLKB 		// Inverter Control for RTSB: asserted = 0 = don't invert
		+ mOPR_CTLA			// assert aux signal on pin header A
		+ mOPR_CTLB			// assert aux signal on pin header B
		+ mOPR_INVA 		// Inverter Control for input signals port A: asserted = 0 = don't invert
		+ mOPR_INVB,		// Inverter Control for input signals port B: asserted = 0 = don't invert

	ROPR_value
		= 0,

// Interupt Mask Register IMR:
	IMR_value
		= !mIMR_TXA_ready	// TxA ready
		+ !mIMR_RXA_ready	// RxA ready
		+ !mIMR_RXA_break	// RxA break change
		+  mIMR_CT_ready	// C/T expired		<-- the only interrupt actually used!
		+ !mIMR_TXB_ready	// TxB ready
		+ !mIMR_RXB_ready	// RxB ready
		+ !mIMR_RXB_break	// RxB break change
		+ !mIMR_IP_changed,	// Input port change

// Auxilliary Control Register:
	ACR_value
		= 0b0000		// 4 bits: 	selects which bits of the input port change register (IPCR)
						//		   	cause the interrupt status register (ISR) bit-7 to be set.
		+ 0b111<<4		// 3 bits: 	Counter/Timer Mode and Clock Source:
						//			Crystal or External Clock (XTAL1/Clk) Divided by 16
		+ 0<<7,			// Baud rate table select

// Mode Register 0:
	MR0_value
		= 0<<0			// 1: baudrate table 1	MUST BE ORED IN!
		+ 0<<1			// FACTORY TEST MODE
		+ 0<<2			// 1: baudrate table 2	MUST BE ORED IN!
		+ 0<<3			// NOT USED
		+ 0b10<<4		// TxD irpt trigger level: 12 of 16 bytes in FIFO are empty
		+ 0 << 6		// RxD irpt trigger level: 6 bytes in FIFO ((+MR1.bit6))
		+ 1 << 7,		// receiver timeout watchdog timer

// Mode Register 1:
	MR1_value
		= 0b11 << 0		// 8 bit
		+ 0 << 2		// if not in multidrop mode: 0 = even parity
		+ 0b10 << 3		// no parity
		+ 0 << 5		// data error mode: 0 = single character
		+ 1 << 6		// RxD trigger level: 6 bytes in FIFO ((+MR0.bit6))
		+ 0 << 7,		// no receiver RTS flow control

// Mode Register 2:
	MR2_value
		= 0b0111 << 0	// stop bit length: 1.000
		+ 0 << 4		// no transmitter CTS flow control
		+ 0 << 5		// no auto transmit RTS
		+ 0b00 << 6 	// no loopback mode
;