I.2.2 The GAL22V10

The GAL22V10 is the successor of the GAL16V8 and GAL20V8. This second
generation of GALs are much more flexible and better to program.

At first the pin designations:

                          GAL22V10
                         ---- ----
      Clock and Input   1|       |24  +5V
                Input   2|       |23  Configurable Output Cell
                Input   3|       |22  Configurable Output Cell
                Input   4|       |21  Configurable Output Cell
                Input   5|       |20  Configurable Output Cell
                Input   6|       |19  Configurable Output Cell
                Input   7|       |18  Configurable Output Cell
                Input   8|       |17  Configurable Output Cell
                Input   9|       |16  Configurable Output Cell
                Input  10|       |15  Configurable Output Cell
                Input  11|       |14  Configurable Output Cell
                GND    12|       |13  Input
                         ---------

The GAL22V10 has ten OLMCs, whereas the GAL16V8 and GAL20V8 has "only"
eight of them. GAL22V10's OLMCs are not as complex (and complicated
to understand) as the OLMCs of the 16V8 and 20V8 GALs. But nevertheless
there are less restrictions.

For each OLMC of a GAL22V10 are just two bits which can be programmed,
the S0- and S1-bit. The S0-bit does the same as the XOR-bit of the
GAL16V8 and GAL20V8. It determines whether an output is active high or
active low.
Just for remembrance:
        XOR (S0) = 0 : Output is active LOW
        XOR (S0) = 1 : Output is active HIGH

The S1-bit does the same as the AC1-bit of the 16V8/20V8 GALs. It determins
whether the OLMC is used as registered-output or as tristate output.
For each output and for each type of output you can define a tristate enable.
So you can define a tristate enable for registered outputs too. This is
another difference to the 16V8/20V8 GALs, because there you can switch
just all registered outputs or non to high impetance by use of the /OE
pin (operation mode 3).

Pin 1 of the GAL22V10 can be both at the same time a "normal" input and
the clock-input for the registers.

There are two additional signals within this GAL, but they are not connected
to any pin, they are internal signals. These are AR (asynchronous reset) and
SP (synchronous preset). These signals are for the registered outputs which
can be controlled by use of the AR and SP. AR resets the registered outputs
when it becomes true, independent from the clock-signal at pin 1 of the GAL
(asynchronous). SP sets the registered output when it becomes true and
when a LOW-HIGH transition of the clock is detected (synchronous).


Another feature of the GAL22V10 is that the amount of rows which are
connected to an OLMC is not constant. The number of rows connected to
an OLMC is between 9 and 17(!).
Here is a table which shows the exactly number of OLMC's rows:

        OLMC at pin |  number of rows from
                    |   the logic-matrix
        ------------+----------------------
             23     |         9
             22     |        11
             21     |        13
             20     |        15
             19     |        17
             18     |        17
             17     |        15
             16     |        13
             15     |        11
             14     |         9


You have to consider that for each OLMC one row is needed for the
tristate enable again. So you can use 8, 10, 12, 14 or 16 product
terms for the output definition.