Feedback lines D0 and D15: attach to ALU result bus?

Series resistor in S_DO to frontpanel := 1k

Div.FF reset output 

Reset line clocked/synchronized to control unit reset

connect d2ar.clk to d2a.clk?

halt opcode: halt in other clock phase

cmd_lo.clk: OR with D14 on ARegs and DRegs board