page1
Display Control Signals
CLK/1
CLK/4
Attiny out
!CLK_EN
DE
Addr-1
Addr in
Data out
0
0
0
1
2
3
4
4
0
0
0
0
1
2
3
4
FPD Clk
0
0
0
0
1
2
3
4
FPD in
dis
dis
dis
D0
D1
D2
D3
dis
4
4
4
5
6
7
8
9
4
4
4
4
5
6
7
8
4
4
4
4
5
6
7
8
dis
dis
dis
D4
D5
D6
D7
dis
CLK/1 64 MHz clock after buffering
CLK/4 16 MHz clock after 74AC163: input clock for ATtiny2313
FPD Clk 64 MHz clock after 2nd inverter: input clock for FPD transmitter
ATtiny out Output of ATtiny port pin. exact toggle position unknown. Note: AVR instructions start at rising clock
!CLK_EN Pixel clock enable signal: from ATtiny port pin, after 74AC74, which is clocked by CLK/4
DE FPD Display Enable: inverted and delayed !CLK_EN signal
Addr-1 Output address of the pixel address counters. Clocked by CLK/1, counting enabled by !CLK_EN
Addr in Input address to the RAMs: synchronized with 74AV574 clocked by CLK/1. Addr in is Addr-1 of prev. cycle
Data out Output data of RAMs, valid after 12ns until 3ns after address going invalid: 6ns valid data
FPD in The FPD transmitter latches the data on the falling edge of the clock: 'dis' indicates that the latched DE signal is 'false'
5ns
NOTE: evtl. kann man auch CLK/1 direkt als FPD Clk verwenden. Jumper Option vorsehen! dann 15ns RAM möglich?