This file is from the book: Microprocessor Technology ISBN 0835943925 Scan done by: Alvin Albrecht aralbrec@concentric.net OCR , retyping, and checking done by: Vaggelis Kapartzianis zx32@usa.net taken from Thanks to you guys for this great work :-) LEGEND IO - internal CPU Operation MR - Memory Read ODL - Operand Data Read of Low Byte MRH - Memory Read of High Byte PR - Port Read MRL - Memory Read of Low Byte PW - Port Write MW - Memory Write SRH - Stack Read of High Byte MWH - Memory Write of High Byte SRL - Stack Read of Low Byte MWL - Memory Write of Low Byte SWH - Stack Write of High Byte OCF - Op Code Fetch SWL - Stack Write of Low byte ODH - Operand Data Read of High Byte ( ) - Number of T-States in that Machine Cycle Z80 INSTRUCTION BREAKDOWN BY MACHINE CODE INSTRUCTION BYTES M1 M2 M3 M4 M5 _______________________________________________________________________________________________ LD r,s 1 OCF(4) LD r,n 2 OCF(4) OD(3) LD r,(HL) 1 OCF(4) MR(3) LD (HL),r 1 OCF(4) MW(3) LD r,(IX+d) 3 OCF(4)+OCF(4) OD(3) IO(5) MR(3) LD (IX+d),r 3 OCF(4)+OCF(4) OD(3) IO(5) MW(3) LD (HL),n 2 OCF(4) OD(3) MW(3) LD A,(dd) 1 OCF(4) MR(3) LD (dd),A 1 OCF(4) MW(3) LD A,(nn) 3 OCF(4) ODL(3) ODH(3) MR(3) LD (nn),A 3 OCF(4) ODL(3) ODH(3) MW(3) LD A,I LD A,R LD I,A LD R,A 2 OCF(4)+OCF(5) LD dd,nn 3 OCF(4) ODL(3) ODH(3) LD IX,nn 4 OCF(4)+OCF(4) ODL(3) ODH(3) LD HL,(nn) 3 OCF(4) ODL(3) ODH(3) MRL(3) MRH(3) LD (nn),HL 3 OCF(4) ODL(3) ODH(3) MWL(3) MWH(3) LD dd,(nn) 4 OCF(4)+OCF(4) ODL(3) ODH(3) MRL(3) MRH(3) LD (nn),dd 4 OCF(4)+OCF(4) ODL(3) ODH(3) MWL(3) MWH(3) LD IX,(nn) 4 OCF(4)+OCF(4) ODL(3) ODH(3) MRL(3) MRH(3) LD (nn),IX 4 OCF(4)+OCF(4) 0DL(3) ODH(3) MWL(3) MWH(3) LD SP,HL 1 OCF(6) LD SP,IX 2 OCF(4)+OCF(6) PUSH qq 1 OCF(5) SWH(3) SWL(3) PUSH IX 2 OCF(4)+OCF(5) SWH(3) SWL(3) POP qq 1 OCF(4) SRH(3) SRL(3) POP IX 2 OCF(4)+OCF(4) SRH(3) SRL(3) EX DE,HL 1 OCF(4) EX AF,AF' 1 OCF(4) EXX 1 OCF(4) EX (SP),HL 1 OCF(4) SRL(3) SRH(4) SWH(3) SWL(5) EX (SP),IX 2 OCF(4)+OCF(4) SRL(3) SRH(4) SWH(3) SWL(5) LDI,LDD,CPI,CPD 2 OCF(4)+OCF(4) MR(3) MW(5) LDIR,LDDR 2 OCF(4)+OCF(4) MR(3) MW(5) IO(5)* * if BC!=O CPIR,CPDR 2 OCF(4)+OCF(4) MR(3) MW(5) IO(5)* * if BC!=O CPIR,CPDR 2 OCF(4)+OCF(4) MR(3) MW(5) IO(2|5*) * if BC!=O lt. z80-documented.pdf ALU* A,r 1 OCF(4) * ADD ADC SUB SBC AND OR XOR CP ALU* A,n 2 OCF(4) OD(3) ALU* A,(HL) 1 OCF(4) MR(3) ALU* A,(IX+d) 3 OCF(4)+OCF(4) OD(3) IO(5) MR(3) INC,DEC r 1 OCF(4) INC,DEC (HL) 1 OCF(4) MR(4) MW(3) INC,DEC (IX+D) 2 OCF(4)+OCF(4) OD(3) IO(5) MR(4) MW(3) RLCA,RLA,RRCA,RRA CPL,CCF,SCF,NOP HALT,DI,EI,DAA 1 OCF(4) IM0,IM1,IM2,NEG 2 OCF(4)+OCF(4) ADD HL,ss 1 OCF(4) IO(4) IO(3) ADC HL,ss SBC HL,ss ADD IX,pp 2 OCF(4)+OCF(4) IO(4) IO(3) INC,DEC ss 1 OCF(6) INC,DEC IX 2 OCF(4)+OCF(6) ROT* r 2 OCF(4)+OCF(4) * RLC,RL,RRC,RR,SLA,SRA,SRL ROT* (HL) 2 OCF(4)+OCF(4) MR(4) MW(3) ROT* (IX+d) 4 OCF(4)+OCF(4) OD(3) IO(5) MR(4) MW(3) RLD,RRD 2 OCF(4)+OCF(4) MR(3) IO(4) MW(3) BIT,SET,RES b,r 2 OCF(4)+OCF(4) BIT b,(HL) 2 OCF(4)+OCF(4) MR(4) SET,RES b,(HL) 2 OCF(4)+OCF(4) MR(4) MW(3) BIT b,(IX+d) 4 OCF(4)+OCF(4) OD(3) IO(5) MR(4) SET,RES b,(IX+d)4 OCF(4)+OCF(4) OD(3) IO(5) MR(4) MW(3) JR e 2 OCF(4) OD(3) IO(5) 4+4+2+2 JR cc,e 2 OCF(4) OD(3) IO(5)* 4+3 or 4+4+2+2 * if cc true DJNZ,e 2 OCF(5) OD(3) IO(5)* 5+3 or 5+4+2+2 * if B<>0 JP nn JP cc,nn 3 OCF(4) ODL(3) ODH(3) JP (HL) 1 OCF(4) JP (IX) 2 OCF(4)+OCF(4) CALL nn CALL cc*,nn 3 OCF(4) ODL(3) ODH(4) SWH(3) SWL(3) * if cc true CALL cc*,nn 3 OCF(4) ODL(3) ODH(3) * if cc false RET 1 OCF(4) SRL(3) SRH(3) RET cc 1 OCF(5) SRL(3)* SRH(3)* * if cc true RETI 2 OCF(4)+OCF(4) SRL(3) SRH(3) RST p 1 OCF(5) SWH(3) SWL(3) IN A,(n) 2 OCF(4) OD(3) PR(4) IN r,(c) 2 OCF(4)+OCF(4) PR(4) INI,IND 2 OCF(4)+OCF(5) PR(4) MW(3) INIR,INDR 2 OCF(4)+OCF(5) PR(4) MW(3) IO(5) OUT (n),A 2 OCF(4) OD(3) PW(4) OUT (C),r 2 OCF(4)+OCF(4) PW(4) OUTI,OUTD 2 OCF(4)+OCF(5) MR(3) W(4) OTIR,OTDR 2 OCF(4)+OCF(5) MR(3) PW(4) IO(5) INTERRUPTS NMI _ OCF(5)* SWH(3) SWL(3) * opcode ignored MODE 0 - INTA(6)* ODL(3)* ODH(4)* SWH(3) SWL(3) * CALL supplied MODE 0 - INTA(6)* SWH(3) SWL(3) * RST supplied MODE 1 INTA(7)* SWH(3) SWL(3) * RST 38H internal MODE 2 - INTA(7)* SWH(3) SWL(3) MRL(3)* MRH(3)* * vector supplied