The clock circuit generates 4 clock phases:

	phase1: prepare phase2
	phase2: fetch command
	phase3: prepare phase4
	phase4: execute command

Opcodes are executed in two cycles of 2 clock phases:

	FETCH = phase1 and phase2
	EXEC  = phase3 and phase4

	phase1: prepare signals for phase2
	phase2: CMD = (PC++)
	phase3: prepare signals for phase4
	phase4: activate signals to perform CMD

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Reg.Addr.OE
	1:	PC
	2: 	any
	3:	set by CMD
	4:	any

Reg.Data.OE
	1:	any, not MEM
	2:	any, not MEM
	3:	set by CMD
	4:	any, not MEM

Addr.FF.E:
Data.FF.E:
these serve as the 1st stopper
	1:	on
	2:	off
	3:	on
	4:	off

Data.FF.OE:
	1:	as for phase2		--> prepare
	2:	off					--> memory read
	3:	as for phase4		--> prepare
	4:	off if Mem.Data.OE	--> memory read
		off if CMD = FUNC	--> optional
		else on

MEM.RD:
	1:	off
	2:	on					--> read CMD
	3:	off
	4:	on if Mem.Data.OE	--> memory read

MEM.WR:
	1:	off
	2:	off
	3:	off
	4:	on if Mem.Data.LE	--> memory write

ALU.CYin:
	1:	on
	2:	on					--> increment for CMD = (PC++)
	3:	set by CMD
	4:	set by CMD

ALU.ffff:
boolean function results
	1:	0000
	2:	0000				--> increment for CMD = (PC++)
	3:	set by CMD
	4:	set by CMD

ALU.ARITH.OE:
	1:	on
	2:	on					--> increment for CMD = (PC++)
	3:	set by CMD
	4:	set by CMD

ALU.BOOL.OE:
	1:	off
	2:	off
	3:	set by CMD
	4:	set by CMD

ALU.SR.E:
	tbd.

Reg.Addr.LE:
this is the 2nd stopper
	1:	off
	2:	on: PC
	3:	off
	4:	on: set by CMD

Reg.Data.LE:
this is the 2nd stopper
	1:	off
	2:	on: Mem
	3:	off
	4:	on: set by CMD

PC.Reset:
	1:	on = reset
	2:	off
	3:	off
	4:	on = irpt AND bit != D14 AND opcode = "CMD=(IP++)"

PC.Set:
	1:	off
	2:	off
	3:	off
	4:	on = irpt AND bit == D14 AND opcode = "CMD=(IP++)"

Clock.phase1.wait:
	1:	on if RESET

Clock.phase2.wait:
	2:	on if WAIT

Clock.phase4.wait:
	4: 	on if WAIT
		on if CMD = "NN=NN"  		--> HALT