The Clock Circuit also contains Reset and Wait logics and indicator for Wait/Halt

The Clock Circuit generates 4 clock phases:

	!phase1 	M___M___
	!phase2 	_M___M__
	!phase3 	__M___M_
	!phase4     ___M___M

	Phase1: prepare phase2
	Phase2: fetch command
	Phase3: prepare phase4
	Phase4: execute command

The clock can be forced into any phase. this is used for RESET and WAIT.

Reset Circuit:

	generate Power On Reset

RESET line:
	input and output line
	switches clock to and keeps it in phase1 (preparation state)
	clock will immediately switch to phase2 when Reset deactivates

WAIT input:
	a wait may be issued from external I/O or Memory in phase2 or phase4.
	this keeps the clock in state2 if state2 is currently active
	or on state4 if state4 is currently active.

HALT output:
	The HALT command activates WAIT in phase4 until input IRPT is activated.
	So the WAIT input is also the HALT output and can be integrated and shown to the user.