CROSS 27 March 1979 The material used in this specification, including but not limited to construction times and operating speeds, is for informational purposes only. All such material is subject to change without notice. Consequently DEC makes no claim and shall not be liable for its accuracy. This document describes the operational procedures for CROSS, an assembler which operates on the DECsystem-10/20 systems, translating source code for 6502, 6800, 8080, 8085, Z80, 1802, F8[future], and 8008 micro-processors into binary files suitable for absolute load. All of the appendices to this manual and the index were constructed by Joseph M. Newcomer, Carnegie-Mellon University Computer Science Department. CROSS-Microcomputer cross assembler 1 1. Introduction CROSS is an assembler which operates on the DECsystem-10/20 and assembles code for many currently available micro-processors. With the exception of the variations listed in this manual, CROSS implements the features of the PDP-11 macro assembler for RSX-11D. No attempt was made to provide source compatibility between CROSS and other micro- processor assemblers. Rather, CROSS has been designed to provide consistent, powerful features for all of the mnemonics associated with each micro-processor. While CROSS is designed to be language compatible with the MACRO-11 language, its PDP-10 operating environment necessitates a PDP-10 style operating procedure. Expression evaluation has been updated to provide the following features: - Default radix is decimal. - @ indicates octal radix, same as to ^O - % indicates binary (6502/6800 only), same as to ^B - %nn indicates register value nn (all others) - $ indicates hexidecimal radix - ^ indicates that the evaluated expression is to be divided by 256. (high byte) The assembler makes two passes over the source, outputting the binary and listing files during pass two and appending a symbol or cross reference table to the listing file. PDP-10 memory is dynamically allocated for large symbol table storage and macro storage. Introduction CROSS-Microcomputer cross assembler 2 2. Syntax differences The syntax of CROSS is more compatible with that of MACRO-11 than that of most manufacturer's assemblers. This means that you will not be able to compile straight 8080, Z80, 6502 or 6800 code with this assembler. However, the transliterations are reasonably straightforward and are described for each machine in the appendices. In general, you must specify registers with a %-directive. The machine which differs most from the manufacturer's specification of an assembler syntax is the Zilog Z80. This is because CROSS implements the Z80 syntax as a superset of the 8080 syntax. Consequently, the syntax of most operations follows that of the 8080. In addition, some Z80 mnemonics conflicted with 8080 mnemonics; the Z80 has been assigned new mnemonics where these conflicts existed. Any Z80 operation which has no 8080 counterpart has also been assigned a mnemonic; some correspond to the Zilog specification (wherever this was possible) and most do not. Consequently, a complete cross-reference between the Zilog syntax and the CROSS transliteration has been provided. Syntax differences CROSS-Microcomputer cross assembler 3 3. Operating procedures 3.1 Loading CROSS CROSS is run by typing the monitor command: @CROSS ;tops20 .R CROSS ;tops10 3.2 Initial dialogue When the assembler is ready to accept the user's command string, it types an asterisk. The user must now type the command string on the same line. The general form of the command string is: binary output, listing output _ source input(s) In addition, the command(s) may be stored in a file (default extension .CCL) and read in by specifying: @filename Each input/output specification consists of the group: dev:filnam.Ext[proj.,prog.]/switch:arg - dev is: DSK for disk PTR for paper tape reader PTP for high speed punch TTY for the user's teletype LPT for a queued line printer - If not specified, the device is assumed to be the disk. Other system devices may also be used, depending upon the system configuation. - filnam is the file name of the appropriate file. - ext is the file name extension for that file. If is not specified, the assumptions are: Operation CROSS-Microcomputer cross assembler 4 binary string: .BIN (absolute) listing string: .LST source string: .M65 (MOS 6502) .M68 (Motorola 6800) .M80 (8080/Z80/8085) .M88 (8008 , 8080 mnemonics) .M08 (8008 , Intel mnemonics) .M18 (CPD1802 , COSMAC) .MF8 (Fairchild F8) [future] - [proj.,prog.] is the project-programmer number assigned for the disk area to be used. If not specified, the user's local area is assumed. Once specified, the number pair becomes the new default assumption for the following files. (Use translate command on TOPS20) At CMU, the CMU PPN format is accepted. - Switches are specified by preceding each with a slash character. Switch arguments are preceded by colons. In addition to explicit specifications of the switches, a default set of switches may be specified with a SWITCH.INI file (chapter 6, page 11). /M65 source is 6502 code /M68 source is 6800 code /M80 source is 8080, 8085 or Z80 code /M88 source is 8008 using 8080 compatible mnemonics /M08 source is 8008 original Intel mnemonics /M18 source is 1802 code (RCA COSMAC) /MF8 source is Fairchild F8 [future] Operation CROSS-Microcomputer cross assembler 5 /LI simulate .LIST directive (see chapter 4). /NL simulate .NLIST directive (see chapter 4). /EN simulate .ENABL directive (see chapter 5). /DS simulate .DSABL directive (see chapter 5). /CRF append cross reference table to the listing files (see chapter 4). /PTP binary output is ASCII coded hex /N suppress error messages and expanded summary to the teletype. /OCT listing format in octal - hex is default /I output binary in image mode (one byte per 36 bit PDP-10 word). This switch must be used to copy directly to paper tape. /P pack binary output. This is the default case and the switch is not needed. /CDR simulate card reader input. This is actually independent of the physical input device but causes the assembler to ignore all characters on a column after the 72nd. /SOL sequence output lines (see chapter 4). /GNS generate new source (see chapter 4). /NSQ suppress listing of PDP-10 style seq. Numbers. /EQ equate the following symbols to zero. This is a method for introducing conditional arguments without creating special parameter tapes. "/EQ:sym1:sym2" is the equivalent of the source statements "sym1=0" and "sym2=0". Operation CROSS-Microcomputer cross assembler 6 4. Listing control CROSS has two categories of listing controls: MACRO-11 compatible, which may be specified either in source statements or in the command string, and a superset which is limited to the command string. 4.1 Source statement listing control Listings are controlled at source statement level through the use of the .LIST and .NLIST directives. These are complementary in that any function which can be enabled by a .LIST can be disabled by a .NLIST. To reduce redundancy, the following descriptions will emphasize the .LIST while implying the .NLIST complement. The following are the allowable arguments for the .LIST directive along with the default settings (li for .LIST and nl for .NLIST): The first group controls intra-line listing. Suppression of any of these will cause the assembler to utilize the space by moving the remainder of the line over. SEQ list the sequence numbers. These numbers represent the source line numbers and are replaced by the nesting level in parentheses for generated lines (macros, etc.). LOC list the value of the location counter. BIN list the binary code generated by the assembler. SRC list the source statement. This is included primarily for completeness. COM list the comment field. BEX list binary code which requires more than one listing line. suppression of this is particularly useful in reducing the length of listing required for long .ASCII strings. The following arguments pertain to entire statements: MB list macro binary and call only - no source MD list macro definitions. MC list macro calls. .LIST/.NLIST CROSS-Microcomputer cross assembler 7 ME -nl list macro expansions. The default causes the expansion to be suppressed in the interest of supply economy. ME controls all generated text (.MACRO's, .REPT's, and .IRP's). Caution - due to their dual nature, .REPT's and .IRP's qualify both as definitions and calls. CROSS treats MD and MC as a pair in these cases, suppressing the listing if either is set. CND list conditionals. Suppression causes unsatisfied conditionals and all conditional directives (whether satisfied or not) to be not listed. SYM append a symbol table to the listing file. TTM list in teletype format (one column of binary to a line, truncation after 72 columns). Default setting is determined by the output device specified: enabled if the physical device is TTY: and disabled (line printer mode) in all other cases. TOC-nl list a table of contents during pass one. This consists of the .SBTTL directives being listed at the beginning of the listing file. Each line consists of the line number and all text to the right of the .SBTTL directive. LD-nl list listing directives. Specifically, this causes all .LIST/.NLIST directives which have no arguments to be listed. its primary use is in debugging listing control. .LIST and .NLIST directives with no arguments perform an over- ride function. They control a listing "level" which is decremented for each .NLIST and incremented for each .LIST. The level count is used as a three way switch: 1. Zero (initial condition): no special action. 2. Less than zero: unconditionally suppress the listing except for lines containing errors. 3. Greater than zero: list unconditionally. .LIST/.NLIST are normally paired to return the level count to zero. the .NLIST/.LIST sequence is used to suppress a range which is normally listed, while the .LIST/.NLIST sequence is used to over-ride a range which is normally suppressed, such as in a macro expansion. The level count allows macro .LIST/.NLIST CROSS-Microcomputer cross assembler 8 expansions to use the listing control and return it to its previous state. 4.2 Command string equivalents The command string contains the equivalent of all the above .LIST and .NLIST functions as well as some that are not available at source level. Indeed, many of the source level arguments are of primary interest at command string level but can be used in the source to modify default settings. The command string equivalents of .LIST and .NLIST are /LI and /NL, respectively. Arguments are specified by preceding them with colons. Thus /NL:bex:cnd is the equivalent of .NLIST CND,BEX. In all cases, command string switches override their source level equivalents (as well as previous occurrences in the command string). Effectively, specification of a function in a command string will cause all its source level equivalents (and their complements) to be ignored. i.e. /LI:me would enable the listing of macro expansions and cause all ".LIST/.NLIST ME" directives to be ignored. /LI (no arguments) causes everything to be listed, while /NL suppresses the listing of all but error lines, the symbol table, and the cross reference tables. 4.3 Other listing controls The following swithces are specified in output side of the command string by preceding the mnemonic by a slash: /OCT list in octal - default is hex /N suppress error messages to the teletype (unless it is also the listing device). /CRF append a cross reference table to the listing file. Cross accomplishes this in the following manner: 1. The listing file is generated in the normal way during pass two, using the name specified by the user. 2. Simultaneously, a temporary file (xxxCRF.TMP, where xxx is the job number) is created. This contains encoded cref information. 3. At the end of pass two, the temporary file is read .LIST/.NLIST CROSS-Microcomputer cross assembler 9 and the cref information is integrated into the symbol table. 4. The references are appended to the listing file. if insufficient core was available to build the table, the process is repeated. When through, the temporary file is deleted. The cross reference table format is as follows: 1. The symbol itself. 2. Its symbol table value, unless .NLIST sym was specified. Therefore the symbol table itself is always pre-empted. 3. All references to the symbol, except that no more than one reference to a given source line will be listed. symbols in generated text always refer to the previous source line. 4. Defining occurrences are flagged with a "#". 5. Destructive references are flagged with a "*". These are defined to be all symbols encountered in op-code fields which store into a memory location or a register. 6. As many references per listing line as possible, depending upon the "ttm" mode, are used. This can be increased by suppressing "sym". /SOL Sequence output lines. Listings are normally source oriented: 1. Sequence numbers reflect the source line number. 2. Macro expansion lines have their nesting level, in parentheses, in the sequence number field. 3. Lines containing nothing but a form feed are not listed but cause the sequence number to be incremented. 4. Page numbers reflect physical input pages .LIST/.NLIST CROSS-Microcomputer cross assembler 10 (incremented only upon encountering a form feed). Pages forced by the assembler have a -n to reflect an extension page. i.e. If the assembler had encountered 3 form feeds and was on its third listing page since the last one, it would be "page 4-2". when /SOL is specified, listings are output oriented: 1. Listed lines have consecutive numbers, except for binary extensions. 2. Page numbers reflect the number of pages listed. /GNS Generate a new source. This causes the listing file to take on the appearance of a source file. specifically, it: 1. Suppresses the listing of headers, error flags, summary blocks, and any other output over which the user otherwise would have no control. 2. Simulates a /NL:seq:loc:bin:bex:me. 3. therefore, by itself, it recreates the source file. Normal usage would have supplementary switches following it. i.e. /gns/nl:md:mc /li:me would replace macros, repeats, and irps by their generated code, /gns/nl:cnd would purge conditionals, and /gns/li:seq would be an expensive way of creating a sequence numbered listing of the source file. .LIST/.NLIST CROSS-Microcomputer cross assembler 11 5. Enable/Disable control As an alternative to the proliferation of directives, cross uses one complementary pair, .ENABL/.DSABL, with arguments. Their command string equivalents are /EN and /DS. The relationship between command string and source statement specification, as well as their argument specification, is the same as in .LIST/.NLIST. M85 allow 8085 opcodes (RIM/SIM) in .M80 files Z80 allow z80 opcodes in .M80 files FPT floating point truncation. ".ENABL FPT" is equivalent to ".TRUNC" while ".DSABL FPT" is equivalent to ".ROUND". ABS absolute assembly AMA absolute memory addressing NPP ".ENABL NPP" causes suppression of the output of the following code, while ".DSABL NPP" causes its resumption. ERF error flags can be selectively suppressed (or enabled) by specifying ERF, directly followed by the selected error characters. "/ds:erfzm" would cause "m" and "z" errors to be ignored, "/ds:erf"would cause all errors to be ignored, and "/en:erfa" would cause"a" flags (argument errors) to be flagged. LC lower case to upper case translation of input ** Actually, this is wrong, as REM noted. It should be: ** allow lower case in listing ** .ENABL LC will allow lowercase. -pgs LSB local symbol block TIM timing information - causes number of states to be output on the listing. REG default register names .ENABL/.DSABL CROSS-Microcomputer cross assembler 12 6. User-defined switch defaults CROSS is capable of accepting user-defined switch defaults. Any switches that are valid in a command string may be specified in a special file called SWITCH.INI. When cross is run, it will look for this file in the user's directory. If the file is not found, then standard defaults (as defined elsewhere in this document) are assumed. if SWITCH.INI is found, but no cross switches are found, default settings are assumed. To specify defaults, use the editor of your choice to create a file called SWITCH.INI. This file must contain a line of the following format: CROSS/switch1/switch2...../switchn continuation lines are permitted. Specifically, a line containing a terminal hyphen is assumed to be followed by a continuation line. Of course CROSS does not consider the hyphen to be a part of any switch. Note that this feature is a subset of the facility offered normally by use of SWITCH.INI files. SWITCH.INI CROSS-Microcomputer cross assembler 13 I. 8080 syntax I.1 Machine State The registers for the 8080 are defined as: - %A - the accumulator - %B - register B - %C - register C - %D - register D - %H - register H, high-order memory reference register - %L - register L, low-order memory reference register - %SP - the stack pointer register - %PSW - the processor status, or F register Register pairs are written in the description of each instruction by concatenating two names, e.g., %H%L is the 16-bit value in the HL register pair. Parentheses are sometimes added for visual clarity, e.g., ".(%H%L)". The flags in the status register are represented by: - c - the carry bit - p - the parity bit. True if the last operation had odd parity, false if even parity. - z - the zero bit. True if the last operation had a zero result. - s - the sign bit. True if the last operation had a negative result. - ie - the interrupt enable flag. In each description of an instruction that alters the condition codes, either an explicit assignment is written (e.g., "c_0") or the condition codes are listed in curly brackets. In this case, it is implied that c is set to indicate carry or borrow (arithmentic operations), z is set if the result is zero, s is set if the result is negative, and p is set if the parity is even. I.2 Notation To reduce the size of the description, several notational conventions will be established for desribing the operands: - i - represents an immediate operand which is 8 bits wide. - m - represents a memory operand which is 16 bits wide. - M - represents an implied memory operand addressed by the register pair %H%L. - MEM - represents all of addressible memory. 8080 CROSS-Microcomputer cross assembler 14 - DEV - represents all addressible devices. - v - a special 3-bit value used for the RST instruction - opnd - a general operand, either register or implied memory. For registers, it will be expressed as %r for one of the 8-bit registers, and for memory it will be expressed as M in the instruction syntax and MEM[.(%H%L)] in the description of the instruction. - %rp - a register pair from the set {%B%C, %D%E, %H%L %SP}. These would be written, in the assembler, as %B, %D, %H or %SP. - %rpn - a register pair from the set {%PSW, %A, %B%C, %D%E, %H%L}. Written as %PSW, %B, %D or %H. I.3 Opcodes The opcodes that are recognized for the 8080 are shown below. The function is given in a BLISS-like notation (the dot operator means "contents of"). ACI i %A _ .%A + i + .c; {c,z,s,p} ADC opnd %A _ .%A + opnd + .c ADD opnd %A _ .%A + .opnd; {c,z,s,p} ADI i %A _ .%A + i; {c,z,s,p} ANA opnd %A _ .%A and .opnd; c _ 0; {z,s,p} ANI i %A _ .%A + i; c _ 0; {z,s,p} CALL m MEM[.%SP-1], MEM[.%SP-1] _ .pc; %SP _ .%SP - 2; pc _ m; CC m if .c then CALL m CM m if .s then CALL m CMA %A _ not .%A; {note: c,z,s,p not changed} CMC c _ not .c CMP opnd .%A - .opnd; {c,z,s,p} CNC m if not .c then CALL m CNZ m if not .z then CALL m CP m if not .s then CALL m CPE m if .p then CALL m CPI i .%A - i; {c,z,s,p} CPO m if not .p then CALL m CZ m if .z then CALL m DAA %A _ DecimalAdjust(.%A); {c,z,s,p} DAD %B %H%L _ .(%H%L) + .(%B%C); {c} DAD %D %H%L _ .(%H%L) + .(%D%E); {c} DAD %SP %H%L _ .(%H%L) + .%SP; {c} DCR opnd opnd _ .opnd - 1; {z,s,p} DCX %rp %rp _ .(%rp) - 1 8080 CROSS-Microcomputer cross assembler 15 DI ie _ 0 EI ie_ 1; HLT IN i %A _ .DEV[i]; INR opnd opnd _ .opnd + 1; {z,s,p} INX %rp %rp _ .(%rp) + 1; JC m if .c then pc _ m; JM m if .s then pc _ m; JMP m pc _ m; JNC m if not .c then pc _ m; JNZ m if not .z then pc _ m; JP m if not .s then pc _ m; JPE m if .p then pc _ m; JPO m if not .p then pc _ m; JZ m if .z then pc _ m; LDA m %A _ .MEM[m]; LDAX %B %A _ .MEM[.(%B%C)]; LDAX %D %A _ .MEM[.(%D%E)]; LHLD m %H _ .MEM[m]; %L _ .MEM[m+1]; LXI %rp,m %rp _ m; MOV %r1,%r2 %r1 _ .%r2; MOV m,%r MEM[m] _ .%r; MOV %r,m %r _ .MEM[m]; MVI opnd,i opnd _ i; NOP ; ORA opnd %A _ .%A or .opnd; c _ 0; {z,s,p} ORI i {%A _ .%A or i;}; c _ 0; {z,s,p} OUT i DEV[i] _ .%A; PCHL pc _ .(%H%L); POP %rpn %rpn _ .MEM[.%SP], .MEM[.%SP + 1]; %SP _ .%SP + 2; PUSH %rpn %SP _ .%SP - 2; MEM[.%SP], MEM[.%SP + 1] _ .%rpn; RAL c%A _ .(c%A) ^ 1; RAR c%A _ .(c%A) ^ -1; RC if .c then RET; RET pc _ .MEM[.%SP], .MEM[.%SP+1]); %SP_.%SP + 2; RLC c _ .%A<7,1>; %A _ .%A ^ 1 RM if .s then RET; RNC if not .c then RET; RNZ if not .z then RET; RP if not .s then RET; RPE if .p then RET; RPO if not .p then RET; RRC c _ .%A<0,1>; %A _ .%A ^ -1; RST v CALL v ^ 8; 8080 CROSS-Microcomputer cross assembler 16 RZ if .z then RET; SBB opnd %A _ .%A - .opnd - .c; {c,z,s,p} SBI i %A _ .%A - i - .c; {c,z,s,p} SHLD m MEM[m] _ .%H; MEM[m+1] _ .%L; SPHL %sp _ .(%H%L); STA m MEM[m] _ .%A; STAX %B MEM[.(%B%C)] _ .%A; STAX %D MEM[.(%D%E)] _ .%A; STC c _ 1; SUB opnd %A _ .%A - .opnd; {c,z,s,p} SUI i %A _ .%A - i; {c,z,s,p} XCHG %D <=> %H; %E <=> %L; XRA opnd %A _ .%A xor .opnd; c _ 0; {z,s,p} XTHL MEM[.%SP - 1] <=> %H; MEM[.%SP] <=> %L; 8080 CROSS-Microcomputer cross assembler 17 II. Z80 syntax II.1 Introduction The Z80 portion of CROSS is not intended to correspond to the Zilog syntax; instead, it is treated as an extension of the 8080 operations described in section I. This means that new opcode designators have been invented where appropriate. II.2 Machine State The Z80 registers are designated exactly like the 8080 registers, with the following additions: - %X - index register X (16 bits) - %Y - index register Y (16 bits) - iv - the interrupt vector base address (8 bits) - ra - the dynamic RAM refresh address (8 bits) II.3 Notation The following notational extensions are made to the 8080 description: - b - A bit position, 0-7, for bit operations - opnd - In addition to %r and M, indexed operands are permitted for all instructions which use opnd; these are expressed to the assembler as d(X) or d(Y), where d is an 8-bit displacement. In the description, they are interpreted as ".%X+d" or ".%Y+d". - %rpx - Register pair including %X, i.e., {%B%C, %D%E, %X, %SP} - %rpy - Register pair including %Y, i.e., {%B%C, %D%E, %Y, %SP} II.4 Opcodes The extended opcodes for the Z80 are given below. Those which are underlined are mnemonics which are neither 8080 instructions nor those defined by Zilog for the Z80; they have been invented for CROSS. A complete transliteration from Zilog assembler format to CROSS syntax is given in section II.5. BIT b,opnd z _ not .opnd CCD .%A - .MEM[.(%H%L)]; %H%L _ .(%H%L) - 1; %BC _ .(%B%C) - 1; {z,s,p} CCDR until .%A = .MEM[.(%H%L)] or .(%B%C) = 0 do begin Z80 CROSS-Microcomputer cross assembler 18 .%A - .MEM[.(%H%L)]; %H%L _ .(%H%L) - 1; %B%C _ .(%B%C) - 1 end; {c,z,p} CCI .%A - .MEM[.(%H%L)]; %H%L _ .(%H%L) + 1; %BC _ .(%B%C) - 1; {z,s,p} CCIR until .%A = .MEM[.(%H%L)] or .(%B%C) = 0 do begin .%A - .MEM[.(%H%L)]; %H%L _ .(%H%L) + 1; %B%C _ .(%B%C) - 1 end; {c,z,p} CNO CPO; CO CPE; DADC %rp %HL _ .(%HL) + .%rp + .c; {c,z,n,p} DADX %rpy %X _ .%X + .%rpy; {c,n} DADY %rpx %Y _ .%Y + .%rpx; {c,n} DJNZ i if .%B 0 then pc _ .pc + 2 + i DSBC %rp %H%L _ .%H%L - .%rp - .c; n _ 1; p _ 0; {c,z} EXAF %A%PSW <=> %A'%PSW'; EXX %B%C <=> %B'%C'; %D%E <=> %D'%E'; %H%L <=> %H'%L' IM0 im _ 0; IM1 im _ 1; IM2 im _ 2; IND INDR INI INIR INP JMPR i pc _ .pc + 2 + i; JNO m JPO m; JO m JPE m; JRC i if .c then JR i; JRNC i if not .c then JR i; JRNZ i if not .z then JR i; JRZ i if .z then JR i; LBCD m %B%C _ .MEM[m]; LDAI %A _ .iv; LDAR %A _ .ra; LDD MEM[.(%D%E)] _ .MEM[.(%H%L)]; %D%E _ .(%D%E) - 1; %H%L _ .(%H%L) - 1; %B%C _ .(%B%C) - 1; n _ 0; LDDR until .(%B%C) = 0 do begin MEM[.(%D%E)] _ .MEM[.(%H%L)]; %D%E _ .(%D%E) - 1; %H%L _ .(%H%L) - 1; %B%C _ .(%B%C) - 1; end; LDED m %D%E _ .MEM[m]; LDI .MEM[.(%D%E)] _ .MEM[.(%H%L)]; %D%E _ .(%D%E) + 1; %H%L _ .(%H%L) + 1; %B%C _ .(%B%C) - 1; {p} LDIR until .(%B%C) = 0 do begin MEM[.(%D%E)] _ .MEM[.(%H%L)]; %D%E _ .(%D%E) + 1; %H%L _ .(%H%L) + 1; %B%C _ .(%B%C) - 1; Z80 CROSS-Microcomputer cross assembler 19 end; LIXD m %X _ .MEM[m+1], .MEM[m]; LIYD m %Y _ .MEM[m+1], .MEM[m]; LSPD m %SP _ .MEM[m+1], .MEM[m]; NEG %A _ - .%A; p _ 0; {c,z,s} OUTD OUTDR OUTI OUTIR OUTP PCIX pc _ .%X; PCIY pc _ .%Y; RALR RARR RES b,opnd %opnd _ 0; RETI return from interrupt RETN return from nonmaskable interrupt RLCR RLD decimal arithmetic RNO RPO; RO RPE; RRCR RRD decimal arithmetic SBCD m MEM[m] _ .(%B%C); SDED m MEM[m] _ .(%D%E); SET b,opnd opnd _ 1; SIXD m MEM[m] _ .%X; SIYD m MEM[m] _ .%Y; SLAR SPIX %SP _ .%X; SPIY %SP _ .%Y; SRAR SRLR SSPD m MEM[m] _ .%SP; STAI iv _ .%A; STAR ra _ .%A; XTIX %X <=> MEM[.%SP]; XTIY %Y <=> MEM[.%SP]; II.5 Z80 Transliterations The following transliterations are necessary because of the differences between the Zilog definition of the instructions and the CROSS syntax. This is indexed alphabetically by the Zilog operations in order to facilitate translation of Zilog assembly programs to CROSS. Z80 transliterations CROSS-Microcomputer cross assembler 20 Zilog Cross ADC i ACI i ADC (HL) ADC M ADC HL,rp DADC %rp ADC (IX+d) ADC d(X) ADC (IY+d) ADC d(Y) ADC r ADC %r ADD i ADI i ADD (HL) ADD M ADD HL,rp DAD %rp ADD (IX+d) ADD d(X) ADD (IY+d) ADD d(Y) ADD r ADD %r AND i ANI i AND (HL) ANA M AND (IX+d) ANA d(X) AND (IY+d) ANA d(Y) AND r ANA %r BIT b,(HL) BIT b,M BIT b,(IX+d) BIT b,d(X) BIT b,(IY+d) BIT b,d(Y) CALL m CALL m CALL C,m CC m CALL M,m CM m CALL NC,m CNC m CALL NZ,m CNZ m CALL NZ,m CNZ m CALL P,m CP m CALL PE,m CPE m CALL PO,m CPO m CALL Z,m CZ m CCF CMC CP i CPI i CP (HL) CMP M CP (IX+d) CMP d(X) CP (IY+d) CMP d(Y) CP r CMP %r CPD CCD CPDR CCDR CPI CCI CPIR CCIR CPL CMA DAA DAA DEC (HL) DCR M Z80 transliterations CROSS-Microcomputer cross assembler 21 DEC IX DCX %X DEC IY DCX %Y DEC (IX+d) DCR d(X) DEC (IY+d) DCR d(Y) DEC rp DCX %rp DEC r DCR %r DI DI DJNZ d DJNZ d EI EI EX AF,AF' EXAF EX DE,HL XCHG EX (SP),HL XTHL EX (SP),IX XTIX EX (SP),IY XTIY EXX EXX HALT HLT IM 0 IM0 IM 1 IM1 IM 2 IM2 IN A,i IN i IN r,(c) INC (HL) INR M INC IX INX %X INC IY INX %Y INC (IX+d) INR d(X) INC (IY+d) INR d(Y) INC rp INX %rp IND IND INDR INDR INI INI INIR INIR JP m JMP m JP M,m JM m JP NC,m JNC m JP NZ,m JNZ m JP NZ,m JNZ m JP P,m JP m JP PE,m JPE m JP PO,m JPO m JP Z,m JZ m JR d JMPR d JR M,m JRM m JR NC,m JRNC m JR NZ,m JRNZ m Z80 transliterations CROSS-Microcomputer cross assembler 22 JR NZ,m JRNZ m JR P,m JRP m JR PE,m JRPE m JR PO,m JRPO m JR Z,m JRZ m LD A,(m) LDA m LD A,(BC) LDAX %B LD A,(DE) LDAX %D LD A,i MVI %A,i LD A,r MOV %A,%r LD (m),A STA m LD (m),BC SBCD m LD (m),DE SDED m LD (m),HL SHLD m LD (m),IX SIXD m LD (m),IY SIYD m LD (m),SP SSPD m LD (BC),A STAX %B LD (DE),A STAX %D LD HL,(m) LHLD m LD (HL),i MVI i LD (HL),r MOV %r,M LD I,A STAI LD IX,(m) LIXD m LD IX,m LXI %X,m LD (IX+d),i MVI i,d(X) LD (IX+d),r MOV %r,d(X) LD IY,(m) LIYD m LD IY,m LXI %Y,m LD (IY+d),i MVI i,d(Y) LD (IY+d),r MOV %r,d(Y) LD r,A MOV %r,%A LD r,i MVI %r,i LD r,(HL) MOV %r,M LD r,(IX+d) MOV %r,d(X) LD r,(IY+d) MOV %r,d(Y) LD r,r MOV %r,%r LD BC,(m) LBCD m LD DE,(m) LDED m LD HL,(m) LHLD m LD SP,(m) LSPD m LD IX,(m) LIXD m LD IY,(m) LIYD m LD rp,m LXI %rp,m Z80 transliterations CROSS-Microcomputer cross assembler 23 LD SP,HL SPHL LD SP,IX SPIX LD SP,IY SPIY LDD LDD LDDR LDDR LDI LDI LDIR LDIR NEG NEG NOP NOP OR i ORI i OR (HL) ORA M OR (IX+d) ORA d(X) OR (IY+d) ORA d(Y) OR r ORA %r OUT (i),r OUT i,A OUT i OUTD OUTD OUTDR OUTDR OUTI OUTI OUTIR OUTIR POP IX POP %X POP IY POP %Y POP rp POP %rp PUSH IX PUSH %X PUSH IY PUSH %Y PUSH rp PUSH %rp RES b,(HL) RES b,M RES b,(IX+d) RES b,d(X) RES b,(IY+d) RES b,d(Y) RES b,r RES b,%r RET RET RET M RM RET NC RNC RET NZ RNZ RET NZ RNZ RET P RP RET PE RPE RET PO RPO RET Z RZ RETI RETI RETN RETN RL (HL) RALR M RL (IX+d) RALR d(X) RL (IY+d) RALR d(Y) Z80 transliterations CROSS-Microcomputer cross assembler 24 RL r RALR %r RLA RAL RLC (HL) RLC M RLC (IX+d) RLC d(X) RLC (IY+d) RLC i(Y) RLC r RLC %r RLCA RLC RLD RLD RR (HL) RARR M RR (IX+d) RARR d(X) RR (IY+d) RARR d(Y) RR r RARR %r RRA RAR RRC (HL) RRC M RRC (IX+d) RRC d(X) RRC (IY+d) RRC d(Y) RRC r RRC %r RRCA RRC RRD RRD RST v RST v SBC i SBI i SBC (HL) SBC M SBC HL,rp DSBC %rp SBC (IX+d) SBC d(X) SBC (IY+d) SBC d(Y) SBC r SBC %r SCF STC SET b,(HL) SET b,M SET b,(IX+d) SET b,d(X) SET b,(IY+d) SET b,d(Y) SET b,r SET b,%r SLA (HL) SLAR M SLA (IX+d) SLAR d(X) SLA (IY+d) SLAR d(Y) SLA r SLAR %r SRA (HL) SRAR M SRA (IX+d) SRAR d(X) SRA (IY+d) SRAR d(Y) SRA r SRAR %r SRL (HL) CB3E SRL (IX+d) DDCBdd3E SRL (IY+d) FDCBdd3E SRL r CB?? SUB i SUI i Z80 transliterations CROSS-Microcomputer cross assembler 25 SUB (HL) SUB M SUB (IX+d) SUB d(X) SUB (IY+d) SUB d(Y) SUB r SUB %r XOR i XRI i XOR (HL) XRA M XOR (IX+d) XRA d(X) XOR (IY+d) XRA d(Y) XOR r XRA %r Z80 transliterations CROSS-Microcomputer cross assembler 26 III. 8008 The 8008 is described by two different sets of opcodes. The one set is based upon the 8080 style of coding, and is a subset of the operations. The other set is based upon the original set of 8008 mnemonics as described by Intel. Rather than give complete descriptions of these operations, the user is referred back to the 8080 descriptions. What this section will give is a listing of the available operations and a cross reference to the original 8008 mnemonics. Note that the 8008 is "software compatible" with the 8080; the same mnemonics will produce different bit patterns for the 8008 and the 8080. III.1 8080 subset The instructions which are implemented for the 8008 are: ACI ADC ADD ADI ANA ANI CALL CC CM CNC CNZ CP CPE CPI CPO CZ DCR HLT INR JC JM JMP JNC JNZ JP JPE JPO MOV MVI NOP ORA ORI OUT RAL RAR RC RET RLC RM RNC RNZ RP RPE RPO RRC RZ SBB SBI SUB SUI XRA XRI The set of original 8008 operations are defined as: 8080 Original 8008 ADC ACA, ACB, ACC, ACD, ACE, ACH, ACL ACI ACI ADD ADA, ADB, ADC, ADD, ADE, ADH, ADL ADI ADI CALL CAL CNC CFC CPO CFP CM CFS CNZ CFZ CMP CPA, CPB, CPC, CPD, CPE, CPH, CPL CPI CPI CC CTC CPE CTP CP CTS CZ CTZ DCR DCB, DCC, DCD, DCE, DCH, DCL HLT HLT INR INB, INC, IND, INE, INH, INL IN INP 8008 CROSS-Microcomputer cross assembler 27 JNC JFC JNZ JFZ JPO JFP JM JFS JMP JMP JC JTC JPE JTP JP JTS JZ JTZ MOV LAA, LAB, LAC, LAD, LAE, LAH, LAL, LAM, LBA, LBB, LBC, LBD, LBE, LBH, LBL, LBM, LCA, LCB, LCC, LCD, LCE, LCH, LCL, LCM, LDA, LDB, LDC, LDD, LDE, LDH, LDL, LDM, LEA, LEB, LEC, LED, LEE, LEH, LEL, LEM, LHA, LHB, LHC, LHD, LHE, LHH, LHL, LHM, LLA, LLB, LLC, LLD, LLE, LLH, LLL, LLM MVI LAI, LBI, LCI, LDI, LEI, LHI, LLI, LMI ANA NDA, NDB, NDC, NDD, NDE, NDH, NDL, NDM ANI NDI NOP NOP ORA ORA, ORB, ORC, ORD, ORE, ORH, ORL, ORM ORI ORI OUT OUT RAL,RAR RAL, RAR RET RET RNC RFC RPO RFP RP RFS RNZ RFZ RLC,RRC RLC, RRC SUB SBA, SBB, SBC, SBD, SBE, SBH, SBL, SBM SBI SBI SBC SUA, SUB, SUC, SUD, SUE, SUH, SUL, SUM SUI SUI XRA XRA, XRB, XRC, XRD, XRE, XRH, XRL, XRM 8008 CROSS-Microcomputer cross assembler 28 IV. 1802 IV.1 Machine State D The data register DF The "data flag" register, or carry P 4-bit program counter pointer X 4-bit data counter pointer T 8-bit buffer for P and X Q Q-status output register IV.2 Opcodes The operation codes recognized for the 1802 are: ADC D _ .mem[.R[.X]] + .D + .DF ADCI D _ data8 + .D + .DF ADD D _ .mem[.R[.X]] + .D ADI D _ data8 + .D AND ANI BDF if .DF then R[P]<7,0> _ adr8 BGE BL BM BNF BNQ BNZ BN1 BN2 BN3 BN4 BPZ BQ BR BZ B1 B2 B3 B4 1802 CROSS-Microcomputer cross assembler 29 DEC n R[n] _ .R[n] - 1; DIS GHI GLO IDL INC n R[n _ .R[n] + 1; INP IRX LBDF LBNF LBNQ LBNZ LBQ LBR LBZ LDA LDI LDN LDX LDXA LSDF LSIE LSKP LSNF LSNQ LSNZ LSQ LSZ MARK NBR NLBR NOP OR ORI OUT PHI PLO REQ RET RSHL RSHR SAV SD SDB 1802 CROSS-Microcomputer cross assembler 30 SDBI SDI SEP SEQ SEX SHL SHLC SHR SHRC SKP SM SMB SMBI SMI STR STXD XOR XRI 1802 CROSS-Microcomputer cross assembler 31 V. 6502 V.1 Machine state The machine state is represented by: - c - The carry bit - z - The zero bit, true if result was zero - v - The overflow bit - s - The sign bit, true if result was negative - d - Decimal mode - i - Interrupt disable bit; 0 => interrupts enabled - b - Breakpoint flag; set by BRK instruction trap The machine registers are: - ac - The single accumulator, 8 bits wide - x - 8 bit index register x, preindexes indirect addresses - y - 8 bit index register y, postindexes indirect addresses. - sp - 8 bit stack pointer. - psw - 8 bit processor status word. V.2 Notation The operands are expressed as: - opnd8 - 8 bit operand corresponding to one of the form: - addr - Base page direct (8 bit address). - addr,X - Base page indexed by x; MEM[addr + .x]. - (addr,X) - Indexed indirect by x; (.MEM[addr + .x]). - (addr),Y - Indexed indirect by y; (.MEM[addr] + .y). 6502 CROSS-Microcomputer cross assembler 32 - opnd16 - Any of the following operands in the form: - addr - Extended direct (16 bit address); MEM[addr]. - addr,X - Absolute indexed via x; MEM[addr + .x]. - addr,Y - Absolute indexed via y; MEM[addr + .y]. - opnd - Either opnd8 or opnd16. - i - Immediate data, expressed as #expression. V.3 Syntax The syntax for operands is much like that specified by MOS Technology. Immediate operands are indicated by preceding the operand with a hash mark, #. V.4 Opcodes The opcodes recognized for the Mos Technology 6502 are: ADC opnd ac _ .ac + .opnd + .c; {s,z,c,v} ADC i ac _ .ac + i + .c; {s,z,c,v} AND opnd ac _ .ac and .opnd; {s,z} AND i ac _ .ac and i; {s,z} ASL opnd c,opnd _ opnd ^ 1; {s,z,c} BCC d if not .c then pc _ .pc + 1 + d; BCS d if .c then pc _ .pc + 1 + d;; BEQ d if .z then pc _ .pc + 1 + d;; BIT opnd .ac and .opnd; s _ (.ac and .opnd)<7,1>; v _ (.ac and .opnd)<6,1>; {z} BMI d if .s then pc _ .pc + 1 + d;; BNE d if not .z then pc _ .pc + 1 + d;; BPL d if not .s then pc _ .pc + 1 + d;; BRK MEM[.sp] _ .pc<0,8>; MEM[.sp + 1] _ .pc<8,8>; MEM[.sp + 2] _ .psw; sp _ .sp - 3; pc _ $FFFFFFFE; i _ 1; b _ 1; BVC d if not .v then pc _ .pc + 1 + d;; BVS d if .v then pc _ .pc + 1 + d;; CLC c _ 0; CLD d _ 0; CLI i _ 0; CLV v _ 0; CMP opnd .ac - .opnd; {s,z,c} CPX opnd .x - .opnd; {s,z,c} CPY opnd .y - opnd; {s,z,c} 6502 CROSS-Microcomputer cross assembler 33 DEC ac _ .ac - 1; {s,z} DEX x _ .x - 1; {s,z} DEY y _ .y - 1; {s,z} EOR opnd ac _ .ac - .opnd INC ac _ .ac + 1; {z,s} INX x _ .x + 1; INY y _ .y + 1; JMP m pc _ m; JSR m MEM[.sp] _ .pc<8,8>; MEM[.sp - 1] _ .pc<0,8>; sp _ .sp - 2; pc _ m; LDA opnd ac _ .opnd; {s,z} LDX opnd x _ .opnd; {s,z} LDY opnd y _ .opnd; {s,z} LSR ac,c _ .ac,0 ^ -1; NOP ; ORA opnd ac _ .ac or opnd; {s,z} PHA MEM[.sp] _ .ac; sp _ .sp - 1; PHP MEM[.sp] _ .psw; sp _ .sp - 1; PLA ac _ .MEM[.sp + 1]; sp _ .sp + 1; PLP psw _ .MEM[.sp + 1]; sp _ .sp + 1; ROL opnd c,.MEM[opnd] _ c,.MEM[opnd] rot 1; {s,z,c} ROR opnd c,.MEM[opnd] _ c,.MEM[opnd] rot -1; {s,z,c} RTI psw _ .MEM[.sp + 1]; pc<0,8> _ .MEM[.sp + 2]; pc<8,8> _ .MEM[.sp + 3]; sp _ .sp + 3; pc _ .pc + 1; RTS pc<0,8> _ .MEM[.sp + 1]; pc<8,8> _ .MEM[.sp + 2]; sp _ .sp + 2; pc _ .pc + 1; SBC opnd ac _ .ac - .opnd - (not .c); {s,z,c,v} SEC c _ 1; SED d _ 1; SEI i _ 1; STA opnd MEM[opnd] _ .ac; {s,z} STX opnd MEM[opnd] _ .x; {s,z} STY opnd MEM[opnd] _ .y; {s,z} TAX a _ .x; TAY a _ .y; TSX sp _ .x; TXA x _ .a; TXS x _ .sp; TYA y _ .a; 6502 CROSS-Microcomputer cross assembler 34 VI. 6800 VI.1 Machine State The registers are: - %A - accumulator A - %B - accumulator B - %X - Index register (16 bits) - sp - Stack pointer (16 bits) - pc - The program counter (16 bits) The flags are: - c - Carry - o - Overflow - s - Sign - z - Zero - xc - Auxiliary carry VI.2 Notation - mem - A memory address which can be one of - Base page direct (.MEM[mem], mem 8 bits) - Extended direct (MEM[mem], mem 16 bits) - Indexed (MEM[mem+.%X], mem 8 bits) - memd - A memory address which can be one one of - Extended direct (MEM[memd], memd 16 bits) - Indexed (MEM[memd+.%X], memd 8 bits) - i - An immediate operand, written as #i 6800 CROSS-Microcomputer cross assembler 35 - i16 - A 16-bit immediate operand, written as #i16 - d - A displacement, usually written as an address; CROSS will compute the actual displacement between the current instruction and the destination address. - opnd - A general operand; may be either mem or i. When interpreted as a value, ".opnd" may represent either .MEM[mem] or i. Please excuse the somewhat sloppy notation; it makes the description more compact. - sr - The status register which holds c,z,s,o,xc. VI.3 Syntax Immediate operands are written with a # symbol, e.g. ADDA #$F9 ; Adds hex F9 to A Indexing is specified by writing ",X" after the operand. The operand must be a value which will fit in 8 bits. foo==$10 ADDA foo,X VI.4 Opcodes ABA %A _ .%A + .%B; {c,z,s,o,xc} ADCA opnd %A _ .%A + .opnd + .c; {c,z,s,o,xc} ADCB opnd %B _ .%B + .opnd + .c; {c,z,s,o,xc} ADDA opnd %A _ .%A + .opnd; {c,z,s,o,xc} ADDB opnd %B _ .%b + .opnd; {c,z,s,o,xc} ANDA opnd %A _ .%A + .opnd; o_0; {z,s} ANDB opnd %B _ .%B + .opnd; o_0; {z,s} ASL memd c_.memd<7,1>; memd_.memd^1; o_.s xor .c; {z,s} ASLA c_.%A<7,1>; %A_.%A^1; o_.s xor .c; {z,s} ASLB c_.%B<7,1>; %B_.%B^1; o_.s xor .c; {z,s} ASR memd c_.memd<0,1>; memd_.memd ash -1; o_.s xor .c; {z,s} ASRA c_.%A<0,1>; %A_.%A ash -1; o_.s xor .c; {z,s} ASRB c_.%B<0,1>; %B_.%B ash -1; o_.s xor .c; {z,s} BCC d if not .c then BRA d; BCS d if .c then BRA d; BEQ d if .z then BRA d; BGE d if not (.o xor .s) then BRA d; BGT d if not (.z or (.s xor .o)) then BRA d; 6800 CROSS-Microcomputer cross assembler 36 BHI d if not (.c or .z) then BRA d; BITA mem .%A and .mem; o _ 0; {z,s} BITB mem .b and .mem; o _ 0; {z,s} BLE d if .z or (.s xor .o) then BRA d; BLS d if .c or .z then BRA d; BLT if .s xor .o then BRA d; BMI d if .s then BRA d; BNE d if not .z then BRA d; BPL d if not .s then BRA d; BR d BRA d; BRA d pc _ .pc + 2 + d; BSR d MEM[.sp] _ .pc<0,8>; MEM[.sp - 1] _ .pc<8,8>; sp _ .sp - 2; pc _ .pc + d + 2; BVC d if not .o then BRA d; BVS d if .o then BRA d; CBA .%A - .%B; {c,z,s,o} CLC c_0; CLI ie _ 0; CLR memd memd_0; c_0; z_1; s_0; o_0; CLRA %A _ 0; c_0; z_1; s_0; o_0; CLRB %B _ 0; c_0; z_1; s_0; o_0; CLV o _ 0; CMPA opnd .%A - .opnd; {c,z,s,o} CMPB opnd .%B - .opnd; {c,z,s,o} COM memd memd_~.memd; c_1; o_0; {s,z} COMA %A_~.%A; c_1; o_0; {s,z} COMB %B_~.%B; c_1; o_0; {s,z} CPX memd %X<0,8>-.(memd+1); %X<8,8>-.memd; {s,z,o} DAA decimal arithmetic DEC memd memd_.memd-1; {s,z,o} DECA %A _ .%A - 1; {s,z,o} DECB %B _ .%B - 1; {s,z,o} DES sp _ .sp - 1; DEX %X _ .%X - 1; {z} EORA opnd %A_%A xor .opnd; o_0; {s,z} EORB opnd %B_%B xor .opnd; o_0; {s,z} INC memd memd_.memd+1; {s,z,o} INCA %A _ .%A + 1; {s,z,o} INCB %B _ .%B + 1; {s,z,o} INS sp _ .sp + 1; INX %x _ .%X + 1; {z} JMP mem pc _ mem; JSR mem MEM[.sp]_.pc<0,8>; MEM[.sp-1]_.pc<8,8>; sp_.sp-2; pc_mem; LDAA 6800 CROSS-Microcomputer cross assembler 37 LDAB LDS mem sp<8,8> _ .mem; sp<0,8> _ .(mem + 1); o _ 0; {z,s} LDS i16 sp _ i16; {s,z} LDX opnd %X<8,8> _ .opnd; %X<0,8> _ .(opnd + 1); o _ 0; {z,s} LSRA LSRB NEG memd memd _ 0 -.memd; {c,s,z,o} NEGA %A _ 0 - .%A; {c,s,z,o} NEGB %B _ 0 - .%B; {c,s,z,o} NOP ; ORAA ORAB PSHA PSHB PULA PULB ROL ROLA ROLB ROR RORA RORB RTI RTS SBA %A _ .%A - .%B; {c,z,s,o} SBCA opnd %A _ %A - .opnd - .c; {c,z,s,o} SBCB opnd %B _ .%B - .opnd - .c; {c,z,s,o} SEC c _ 1; SEI ie _ 1; SEV o _ 1; STAA STAB STS mem mem _ .sp<8,8>; (mem + 1) _ .sp<0,8>; o_0; {s,z} STX mem mem _ .%X<8,8>; (mem + 1) _ .%X<0,8>; o_0; {s,z} SUBA opnd %A _ .%A - .opnd; {c,s,z,o} SUBB opnd %B _ .%B - .opnd; {c,s,z,o} SWI software interrupt TAB %B _ .%A; o_0; {s,z} TAP sr _ .%A; {c,z,s,o,xc} TBA %A _ .%B; o_0; {s,z} TPA %A _ .sr TST memd c _ 0; z _ .memd = 0; s _ .memd < 0; o _ 0; TSTA c _ 0; z _ .%A = 0; s _ .%A < 0; o _ 0; TSTB c _ 0; z _ .%B = 0; s _ .%B < 0; o _ 0; 6800 CROSS-Microcomputer cross assembler 38 TSX %X _ .sp + 1; TXS sp _ .%X - 1; WAI MEM[.sp]_.pc<0,8>; MEM[.sp-1]_.pc<8,8>; MEM[.sp-2]_.%X<0,8>; MEM[.sp-3]_%X<8,8>; MEM[.sp-4]_.%A; MEM[.sp-5]_.%B; MEM[.sp-6]_.sr; sp_.sp-7; 6800 CROSS-Microcomputer cross assembler 39 VII. Compiler directives The following compiler directives and their presumed meanings are described briefly here. This is only a refresher for those who have read the DEC assembler description. .ABS Compile non-relocatable (absolute) code. .ADDR Generates a 16-bit address with the bytes in the proper order, i.e., . .ASCII ASCII string delimited by paired markers. .ASCIZ ASCIZ string delimited by paired markers and supplied with terminal null byte. .ASECT Begin an absolute (non-relocatable) control section. .BLKB Allocate space for a number of bytes as specified by the operand. .BLKW Allocate space for a number of words as specified by the operand. .BYTE Each expression supplied will be stored in a single byte. .CSECT Enter a Csect. .DEPHA Dephase; leave .PHASE control area. .DSABL See chapter 5. .ENABL See chapter 5. .END End of program. .ENDC End of conditional; paired with .IF. .ENDM End of macro definition or repeat; paired with .MACRO, .IRP, .IRPC, .REPT. .ENDR End of repetition; paired with .REPT; equivalent to .ENDM in this context. .EOT End-of-tape; assembler will wait for next tape to be loaded Compiler directives CROSS-Microcomputer cross assembler 40 (paper tape hackers only). .EQUIV ? .ERROR x;text Causes an error message to be issued. The optional expression x is evaluated and output if present. .FLT2 ? .FLT4 ? .GLOBL ? .IF Enter a conditional. .IFDF .IFDF true if symbol is defined. See also .IFNDF. .IFEQ .IFEQ true if expression evaluates to zero. .IFF Begins body of conditional if enclosing condition was false. .IFG .IFG true if expression greater than zero. .IFGE .IFG true if expression greater than or equal to zero. .IFGT Same as .IFG .IFL .IFL true if expression is negative. .IFLE .IFLE true if expression is negative or zero. .IFLT Same as .IFL. .IFNDF .IFNDF true if symbol is undefined. .IFNE .IFNE true if expression is non-zero. .IFNZ Same as .IFNE .IFT Begins body of conditional if enclosing condition was true. .IFTF Text from here to the next .IFT, .IFF or .IFTF or the end of the conditional will be included independent of the value of Compiler directives CROSS-Microcomputer cross assembler 41 the condition of the enclosing conditional. .IFZ Same as .IFE .IIF condition, arg, stmnt Immediate if; if condition is met, stmnt is emitted. .IRP sym, Indefinite repeat of body based upon number of parameters in . .IRPC sym,Indefinite repeat of body based upon number of characters in . .LIMIT Reserves two words into which are put the lower and upper boundaries of the code. .LIST Enable listing. .LOCAL ? .MACRO name Begin a macro definition .MCALL Call macros from the system library. .MEXIT Leave macro expansion .NARG sym The symbol is equated to the number of arguments to the macro .NCHR sym, The symbol is equated to the number of characters in .NLIST Turn off listing .NTYPE sym,arg The symbol is equated to the addressing mode of the argument. .PAGE Force a page break .PDP10 Irrelevant .PHASE Assemble code as if it were located according to the argument of this directive. Compiler directives CROSS-Microcomputer cross assembler 42 .PRINT Print the text which follows on the terminal. .PSECT .RADIX Change the radix to the value specified to this directive. .RAD50 Each argument is converted to a radix50 representation, whatever that means for a microcomputer. .REM .REPT (.REPT ) Repeat the body of this directive the indicated number of times. .ROUND Perform arithmetic operations with rounding to integer result (see also .TRUNC). .SBTTL Specify subtitle text. .TITLE Specify title text. .TRUNC Perform arithmetic operations with truncation to integer result (see also .ROUND) .WORD Allocate space for each value specified. Each expression evaluates to a word (16 bits). Compiler directives CROSS-Microcomputer cross assembler 43 VIII. Macro quick summary ? When specified with a formal, will cause a compiler-generated symbol to be provided if an actual is not given in that position. ' Internal concatenation character \ When used as an argument, evaluates before performing the actual-formal match. Macro summary CROSS-Microcomputer cross assembler 44 IX. Assembler syntax quick summary <...> Encloses any expression (the assembler's equivalent of parentheses). Expressions are evaluated left-to-right without operator heirarchy. + Addition or unary plus - Subtraction or unary minus * Multiplication / Division & Logical and ! Logical or ; Begins comment field ' Indicates single ASCII character as a term in expressions. ^O Indicates octal number ^B Indicates binary number = Symbol assignment . Current location counter $ Indicates hexadecimal number % Indicates binary number (6502/6800 mode only) ^ If a postfix operator, divides the expression by 256. Assembler summary CROSS-Microcomputer cross assembler 45 Index ! 44 #, in cref 9 $ 1, 44 % 1, 44 %nn, register 1 & 44 ', concatenation 43, 44 * 44 *, in cref 9 + 44 - 44 ., location counter 44 .ABS 39 .ADDR 39 .ASCII 39 .ASCIZ 39 .ASECT 39 .BLKB 39 .BLKW 39 .BYTE 39 .CSECT 39 .DEPHAse 39 .DSABL 5, 11, 39 .ENABL 5, 11, 39 .END 39 .ENDC 39 .ENDM 39 .ENDR 39 .EOT 39 .EQUIV 40 .ERROR 40 .FLT2 40 .FLT4 40 Index CROSS-Microcomputer cross assembler 46 .GLOBL 40 .IF 40 .IFDF 40 .IFEQ 40 .IFF 40 .IFG 40 .IFGE 40 .IFGT 40 .IFL 40 .IFLE 40 .IFLT 40 .IFNDF 40 .IFNE 40 .IFNZ 40 .IFT 40 .IFTF 40 .IFZ 41 .IIF 41 .IRP 41 .IRPC 41 .LIMIT 41 .LIST 4, 6, 7, 41 .LOCAL 41 .MACRO 41 .MCALL 41 .MEXIT 41 .NARG 41 .NCHR 41 .NLIST 5, 6, 7, 41 .NTYPE 41 .PAGE 41 .PDP10 41 .PHASE 41 .PRINT 41 .PSECT 42 .RAD50 42 .RADIX 42 .REM 42 .REPT 42 .ROUND 11, 42 .SBTTL 42 .TITLE 42 .TRUNC 11, 42 .WORD 42 Index CROSS-Microcomputer cross assembler 47 / 44 /CDR 5 /CRF 5, 8 /DS 5, 11 /EN 5, 11 /EQ 5 /GNS 5, 10 /I 5 /LI 4, 8 /M08 4 /M18 4 /M65 4 /M68 4 /M80 4 /M88 4 /MF8 4 /N 5, 8 /NL 5, 8 /NSQ 5 /OCT 5, 8 /P 5 /PTP 5 /SOL 5, 9 1802 4, 28 6502 4, 31 6800 4, 34 72, column 5 8008 4, 26 8080 4, 13 8085 4 ;, comment delimiter 44 <...> 44 = 44 ?, macro argument modifier 43 Index CROSS-Microcomputer cross assembler 48 @, in command 3 @ 1 ABS 11 .ABS 39 Absolute memory addressing 11 .ADDR 39 AMA 11 And, assembler operator 44 .ASCII 39 .ASCIZ 39 .ASECT 39 BEX, listing option 6 BIN, extension 3 BIN, listing option 6 Binary listing option 6 Binary radix 1 .BLKB 39 .BLKW 39 .BYTE 39 Byte, high 1 Card reader simulation 5 CCL file 3 /CDR 5 CND, listing option 7 COM, listing option 6 Command line 3 Comment delimiter 44 Comment listing option 6 Concatenation operator 43, 44 Conditional compilation: .IF 40 Conditional listing option 7 Contents, listing option 7 COSMAC 1802 4, 28 /CRF 5, 8 CRF.TMP file 8 Cross-reference 5 .CSECT 39 Current location counter 44 Decimal radix 1 .DEPHAse 39 Index CROSS-Microcomputer cross assembler 49 /DS 5, 11 .DSABL 5, 11, 39 DSK, device 3 /EN 5, 11 .ENABL 5, 11, 39 .END 39 .ENDC 39 .ENDM 39 .ENDR 39 .EOT 39 /EQ 5 .EQUIV 40 ERF 11 .ERROR 40 Error flags, suppression 11 Error message suppression 5 Extension .BIN 3 Extension .CCL 3 Extension .LST 4 Extension .M08 4 Extension .M18 4 Extension .M65 4 Extension .M68 4 Extension .M80 4 Extension .M88 4 Extension .MF8 4 F8 4 Fairchild F8 4 Floating point truncation 11 .FLT2 40 .FLT4 40 FPT 11 Generate new source 5, 10 .GLOBL 40 /GNS 5, 10 Hex output 5 Hexidecimal radix 1 High byte 1 /I 5 Index CROSS-Microcomputer cross assembler 50 .IF 40 .IFDF 40 .IFEQ 40 .IFF 40 .IFG 40 .IFGE 40 .IFGT 40 .IFL 40 .IFLE 40 .IFLT 40 .IFNDF 40 .IFNE 40 .IFNZ 40 .IFT 40 .IFTF 40 .IFZ 41 .IIF 41 Image mode output 5 Intel 8008 4, 26 Intel 8080 4, 13 Intel 8085 4 .IRP 41 .IRPC 41 LC 11 LD, listing option 7 /LI 4, 8 .LIMIT 41 Line numbers 5 .LIST 4, 6, 7, 41 Listing option BEX 6 Listing option BIN 6 Listing option CND 7 Listing option COM 6 Listing option LD 7 Listing option LOC 6 Listing option MB 6 Listing option MC 6 Listing option MD 6 Listing option ME 6 Listing option SEQ 6 Listing option SRC 6 Listing option SYM 7 Listing option TOC 7 Index CROSS-Microcomputer cross assembler 51 Listing option TTM 7 LOC, listing option 6 .LOCAL 41 Location counter 44 Lower case 11 LPT, device 3 LSB 11 LST, extension 4 /M08 4 M08, extension 4 /M18 4 M18, extension 4 /M65 4 M65, extension 4 /M68 4 M68, extension 4 /M80 4 M80, extension 4 M85 11 /M88 4 M88, extension 4 .MACRO 41 Macro call listing option 6 Macro definition 41 Macro, concatenation 43, 44 MB, listing option 6 MC, listing option 6 .MCALL 41 MD, listing option 6 ME, listing option 6 Memory addressing, absolute 11 .MEXIT 41 MF8 4 MF8, extension 4 MOS 6502 4, 31 Motorola 6800 4, 34 /N 5, 8 .NARG 41 .NCHR 41 New source, generation 5, 10 /NL 5, 8 .NLIST 5, 6, 7, 41 Index CROSS-Microcomputer cross assembler 52 /NPP 11 /NSQ 5 .NTYPE 41 /OCT 5, 8 Octal radix 1, 5 Or, assembler operator 44 Output format 5 /P 5 Packed binary output 5 .PAGE 41 .PDP10 41 .PHASE 41 .PRINT 41 .PSECT 42 /PTP 5 PTP, device 3 PTR, device 3 .RAD50 42 .RADIX 42 Radix 16 1 Radix 2 1 Radix 8 1, 5 Radix, 10 1 Radix, binary 1 Radix, decimal 1 Radix, default 1 Radix, hexidecimal 1 Radix, octal 1 RCA 1802 4, 28 REG 11 Register %nn 1 .REM 42 .REPT 42 RIM, opcode 11 .ROUND 11, 42 .SBTTL 42 SEQ, listing option 6 SIM, opcode 11 /SOL 5, 9 Source listing option 6 Index CROSS-Microcomputer cross assembler 53 Source, new, generation 5, 10 SRC, listing option 6 Suppression of error flags 11 Switch CDR 5 Switch CRF 5, 8 Switch DS 5, 11 Switch EN 5, 11 Switch EQ 5 Switch GNS 5, 10 Switch I 5 Switch LI 4, 8 Switch M08 4 Switch M18 4 Switch M65 4 Switch M68 4 Switch M80 4 Switch M88 4 Switch N 5, 8 Switch NL 5, 8 Switch NPP 11 Switch NSQ 5 Switch OCT 5, 8 Switch P 5 Switch PTP 5 Switch SOL 5, 9 SWITCH.INI 12 SYM, listing option 7 Symbol table listing option 7 Table of contents, listing option 7 Teletype format listing option 7 TIM 11 .TITLE 42 TOC, listing option 7 .TRUNC 11, 42 Truncation 11 TTM, listing option 7 TTY, device 3 .WORD 42 Z80 4, 11, 17 Z80 transliteration 19 Zilog Z80 4, 17 Index CROSS-Microcomputer cross assembler 54 \, macro argument modifier 43 ^, ^ 1, 44 ^B 1, 44 ^O 1, 44 Index