page1
1
2
3
4
5
6
7
8
9
A
Read Cycle
Address
Clock
S0
S1
S2
/AS
/DS
S3
S4
S5
S6
S7
50
CPU Din
/DTACK in
/DTACK
/MEM CE
after 74HCT139
RAM Dout
after /CE
ROM Dout
after /CE
27C512-25
Data in
3 .. 50
max. 50
min. 20
34
70
10
16
max. 10
34
34
25
max. 10
max. 50
16
0
0
0
100
60
0
250
/WR
/RD after 74HCT00
max. 45
250
24
ROM Dout
after /OE
27C512-25
K1-Bus Strobe
after 74HCT138
74ACT138
min. 50
min. 150
18
40
12
18
40
40
12